Patents by Inventor Meng-Liang Lin

Meng-Liang Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210013053
    Abstract: In an embodiment, a package includes: a first redistribution structure; a first integrated circuit die connected to the first redistribution structure; a ring-shaped substrate surrounding the first integrated circuit die, the ring-shaped substrate connected to the first redistribution structure, the ring-shaped substrate including a core and conductive vias extending through the core; a encapsulant surrounding the ring-shaped substrate and the first integrated circuit die, the encapsulant extending through the ring-shaped substrate; and a second redistribution structure on the encapsulant, the second redistribution structure connected to the first redistribution structure through the conductive vias of the ring-shaped substrate.
    Type: Application
    Filed: September 28, 2020
    Publication date: January 14, 2021
    Inventors: Po-Hao Tsai, Techi Wong, Meng-Wei Chou, Meng-Liang Lin, Po-Yao Chuang, Shin-Puu Jeng
  • Patent number: 10804254
    Abstract: Structures and methods of forming fan-out packages are provided. The packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. Embodiments include a cavity preformed in a cavity substrate. Various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. Redistribution structures may also be formed.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Hao Tsai, Techi Wong, Po-Yao Chuang, Shin-Puu Jeng, Meng-Wei Chou, Meng-Liang Lin
  • Publication number: 20200312773
    Abstract: A package structure and a formation method of a package structure are provided. The method includes forming a redistribution structure over a carrier substrate and disposing a semiconductor die over the redistribution structure. The method also includes stacking an interposer substrate over the redistribution structure. The interposer substrate extends across edges of the semiconductor die. The method further includes disposing one or more device elements over the interposer substrate. In addition, the method includes forming a protective layer to surround the semiconductor die.
    Type: Application
    Filed: June 20, 2019
    Publication date: October 1, 2020
    Inventors: Po-Hao TSAI, Meng-Liang LIN, Po-Yao CHUANG, Techi WONG, Shin-Puu JENG
  • Patent number: 10790162
    Abstract: In an embodiment, a package includes: a first redistribution structure; a first integrated circuit die connected to the first redistribution structure; a ring-shaped substrate surrounding the first integrated circuit die, the ring-shaped substrate connected to the first redistribution structure, the ring-shaped substrate including a core and conductive vias extending through the core; a encapsulant surrounding the ring-shaped substrate and the first integrated circuit die, the encapsulant extending through the ring-shaped substrate; and a second redistribution structure on the encapsulant, the second redistribution structure connected to the first redistribution structure through the conductive vias of the ring-shaped substrate.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: September 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Hao Tsai, Techi Wong, Meng-Wei Chou, Meng-Liang Lin, Po-Yao Chuang, Shin-Puu Jeng
  • Publication number: 20200211962
    Abstract: A package structure and method for forming the same are provided. The package structure includes a die structure formed over a first interconnect structure, and the die structure includes a first region and a second region. The package structure includes a dam structure formed on the first region of the die structure, and a second interconnect structure formed over the die structure and the dam structure. The package structure also includes a package layer formed between the first interconnect structure and the second interconnect structure, and the package layer is formed on the second region of the die structure to surround the dam structure.
    Type: Application
    Filed: April 10, 2019
    Publication date: July 2, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Hao TSAI, Techi WONG, Meng-Liang LIN, Yi-Wen WU, Po-Yao CHUANG, Shin-Puu JENG
  • Publication number: 20200135653
    Abstract: Structures and formation methods of a package structure are provided. The method includes forming a conductive structure over a carrier substrate and disposing a semiconductor die over the carrier substrate. The method also includes pressing a protective substrate against the carrier substrate at an elevated temperature to bond the protective substrate to the conductive structure. The method further includes forming a protective layer to surround the semiconductor die.
    Type: Application
    Filed: June 11, 2019
    Publication date: April 30, 2020
    Inventors: Po-Hao TSAI, Hsien-Wen LIU, Shin-Puu JENG, Meng-Liang LIN, Shih-Yung PENG, Shih-Ting HUNG
  • Publication number: 20200105663
    Abstract: In an embodiment, a package includes: a first redistribution structure; a first integrated circuit die connected to the first redistribution structure; a ring-shaped substrate surrounding the first integrated circuit die, the ring-shaped substrate connected to the first redistribution structure, the ring-shaped substrate including a core and conductive vias extending through the core; a encapsulant surrounding the ring-shaped substrate and the first integrated circuit die, the encapsulant extending through the ring-shaped substrate; and a second redistribution structure on the encapsulant, the second redistribution structure connected to the first redistribution structure through the conductive vias of the ring-shaped substrate.
    Type: Application
    Filed: December 3, 2018
    Publication date: April 2, 2020
    Inventors: Po-Hao Tsai, Techi Wong, Meng-Wei Chou, Meng-Liang Lin, Po-Yao Chuang, Shin-Puu Jeng
  • Publication number: 20200105544
    Abstract: Embodiments include forming an interposer having reinforcing structures disposed in a core layer of the interposer. The interposer may be attached to a package device by electrical connectors. The reinforcing structures provide rigidity and thermal dissipation for the package device. Some embodiments may include an interposer with an opening in an upper core layer of the interposer to a recessed bond pad. Some embodiments may also use connectors between the interposer and the package device where a solder material connected to the interposer surrounds a metal pillar connected to the package device.
    Type: Application
    Filed: April 1, 2019
    Publication date: April 2, 2020
    Inventors: Po-Hao Tsai, Ming-Chih Yew, Chia-Kuei Hsu, Shin-Puu Jeng, Po-Yao Chuang, Meng-Liang Lin, Shih-Ting Hung, Po-Yao Lin
  • Publication number: 20200006307
    Abstract: Structures and methods of forming fan-out packages are provided. The packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. Embodiments include a cavity preformed in a cavity substrate. Various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. Redistribution structures may also be formed.
    Type: Application
    Filed: November 16, 2018
    Publication date: January 2, 2020
    Inventors: Po-Hao Tsai, Techi Wong, Po-Yao Chuang, Shin-Puu Jeng, Meng-Wei Chou, Meng-Liang Lin
  • Publication number: 20200006214
    Abstract: A method includes forming an interposer, which includes forming a rigid dielectric layer, and removing portions of the rigid dielectric layer. The method further includes bonding a package component to an interconnect structure, and bonding the interposer to the interconnect structure. A spacer in the interposer has a bottom surface contacting a top surface of the package component, and the spacer includes a feature selected from the group consisting of a metal feature, the rigid dielectric layer, and combinations thereof. A die-saw is performed on the interconnect structure.
    Type: Application
    Filed: August 31, 2018
    Publication date: January 2, 2020
    Inventors: Po-Hao Tsai, Techi Wong, Meng-Wei Chou, Meng-Liang Lin, Po-Yao Chuang, Shin-Puu Jeng
  • Publication number: 20200006176
    Abstract: A method for forming a chip package structure is provided. The method includes disposing a chip over a redistribution structure. The method includes forming a molding layer over the redistribution structure adjacent to the chip. The method includes partially removing the molding layer to form a trench in the molding layer, and the trench is spaced apart from the chip.
    Type: Application
    Filed: November 26, 2018
    Publication date: January 2, 2020
    Inventors: Po-Hao TSAI, Techi WONG, Meng-Wei CHOU, Meng-Liang LIN, Po-Yao CHUANG, Shin-Puu JENG
  • Patent number: 10446522
    Abstract: Semiconductor devices and methods of forming the same are described. An embodiment is a device including a pad on a substrate. A passivation film is on the substrate and covering at least a portion of the pad. A first conductive feature is on the pad and has a planar top surface, with the first conductive feature having a first height as measured from the pad to the planar top surface of the first conductive feature. A second conductive feature is on the passivation film and has a non-planar top surface, with the second conductive feature having a second height as measured from the passivation film to the non-planar top surface of the second conductive feature.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: October 15, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Liang Lin, Cheng-Lin Huang
  • Publication number: 20160307862
    Abstract: Semiconductor devices and methods of forming the same are described. An embodiment is a device including a pad on a substrate. A passivation film is on the substrate and covering at least a portion of the pad. A first conductive feature is on the pad and has a planar top surface, with the first conductive feature having a first height as measured from the pad to the planar top surface of the first conductive feature. A second conductive feature is on the passivation film and has a non-planar top surface, with the second conductive feature having a second height as measured from the passivation film to the non-planar top surface of the second conductive feature.
    Type: Application
    Filed: April 16, 2015
    Publication date: October 20, 2016
    Inventors: Meng-Liang Lin, Cheng-Lin Huang
  • Patent number: 9343419
    Abstract: A package structure includes a first substrate bonded to a second substrate by connecting metal pillars on the first substrate to connectors on the second substrate. A first metal pillar is formed overlying and electrically connected to a metal pad on a first region of the first substrate, and a second metal pillar is formed overlying a passivation layer in a second region of the first substrate. A first solder joint region is formed between metal pillar and the first connector, and a second solder joint region is formed between the second metal pillar and the second connector. The lateral dimension of the first metal pillar is greater than the lateral dimension of the second metal pillar.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: May 17, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Meng-Liang Lin, Jy-Jie Gau, Cheng-Lin Huang, Jing-Cheng Lin, Kuo-Ching Hsu
  • Publication number: 20140167254
    Abstract: A package structure includes a first substrate bonded to a second substrate by connecting metal pillars on the first substrate to connectors on the second substrate. A first metal pillar is formed overlying and electrically connected to a metal pad on a first region of the first substrate, and a second metal pillar is formed overlying a passivation layer in a second region of the first substrate. A first solder joint region is formed between metal pillar and the first connector, and a second solder joint region is formed between the second metal pillar and the second connector. The lateral dimension of the first metal pillar is greater than the lateral dimension of the second metal pillar.
    Type: Application
    Filed: March 6, 2013
    Publication date: June 19, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Meng-Liang Lin, Jy-Jie Gau, Cheng-Lin Huang, Jing-Cheng Lin, Kuo-Ching Hsu