Abstract: A scheme for determining a flipping energy used in a bit-flipping decoder. The flipping energy is determined based on: a weight of at least one check node coupled to a column; a syndrome as a product of a noisy codeword and a parity check matrix; and a hard decision value of a previous iteration and a channel output value associated with the column.

Abstract: A controller estimates optimal read threshold values for a memory device using deep learning. The memory device includes multiple pages coupled to select word lines in a memory region. The controller performs multiple read operations on a select type of page for each word line using multiple read threshold sets, obtains fail bit count (FBC) information associated with each read operation, and determines an optimal read threshold set for each word line based on the FBC information. When optimal read threshold sets for the select word lines are different each other, the controller predicts a best read threshold set using the optimal read threshold sets.

Abstract: Devices, systems, and methods for reducing a latency of a decoder in a non-volatile memory are described. An example method includes receiving a noisy codeword that is based on a transmitted codeword generated from a low-density parity-check (LDPC) code, the LDPC code having an associated parity matrix comprising a plurality of columns of circulant matrices, performing a sorting operation that sorts the plurality of columns of circulant matrices in a descending order of a first quality metric to generate a plurality of sorted columns of circulant matrices, the first quality metric indicative of a number of errors in a corresponding column of circulant matrices, and iteratively processing the plurality of sorted columns of circulant matrices to determine a candidate version of the transmitted codeword.

Abstract: A scheme for determining a flipping energy used in a bit-flipping decoder. The flipping energy is determined based on: a weight of at least one check node coupled to a column; a syndrome as a product of a noisy codeword and a parity check matrix; and a hard decision value of a previous iteration and a channel output value associated with the column.

Abstract: A memory system or a method for estimating channel information to be used for error decoding. The memory system or the method a) performs one or more read operations on a page selected from among the plurality of pages using a target read threshold, b) obtains the target read threshold, a historical read threshold voltage set associated with failed read operations of the selected page, checksum values, and asymmetric ratios of ones count and zeros count which are associated with the historical read threshold voltage set, c) provides the obtained target read threshold, historical read threshold voltage set, checksum values and asymmetric ratios as input information to a neural network, and d) predicts, by the neural network, channel information at the target read threshold based on the input information and a set activation function.

Abstract: A method and a system for operating a deep neural network. In the method and system, a subset of floating-point values are used to represent weights in the DNN; the floating-point values are quantized onto a flexible-power-of-two (FPoT) alphabet; values in the FPoT alphabet are listed in a plurality of regions; and an empty region among the plurality of regions is merged to neighbour regions to output dusters of the weights in merged regions, the merged regions having respective centroids and boundary lines in between.

Abstract: Devices, systems, and methods for performance of an iterative decoder in a non-volatile memory are described. An example method includes receiving a noisy codeword that is based on a transmitted codeword generated from a low-density parity-check (LDPC) code, partitioning a maximum number of iterations of the iterative decoder into a plurality of stages, initializing a set of log likelihood ratios (LLRs) with symmetric LLRs, for each stage of the plurality of stages: performing a message passing algorithm, determining, at a last iteration of the current stage, a hard decision corresponding to a candidate version of the transmitted codeword, determining, based on the hard decision, a set of asymmetric LLRs, and assigning the set of asymmetric LLRs to the set of LLRs, and determining the candidate version of the transmitted codeword using the set of LLRs.

Abstract: Decoding method and memory system that decodes data and estimates a weighted checksum on the decoded data to determine whether the decoding is successful. The weighted checksum is calculated based on a first group and a second group, the first group is associated with weights for high degree nodes of an irregular parity check matrix, and the second group is associated with weights for low degree nodes of the irregular parity check matrix.

Abstract: A controller determines, for each read operation, a mathematical model by using a) a set function of a read threshold voltage set among the plurality of read threshold voltages and b) a set checksum value; determines a polynomial regression model based on the mathematical model; determines a parameter set by using multiple computations between input and output matrices based on the polynomial regression model; and estimates a next read threshold voltage for a next read operation based on the parameter set. The controller computes mathematical operation algorithms to replace a normal multiplication operation, a normal division operation and a normal multiplication followed by division operation.

Abstract: A method and system for LDPC decoding method. In the method and system, an LDPC codeword is decoded using a quasi-cyclic matrix. A first message for variable nodes in a circulant column of the quasi-cyclic matrix and a second message for check nodes belonging to the circulant column are computed. Parity and syndrome are computed using the computed first and second messages. A bit error rate is calculated for both a first mode with no error in a parity portion of a codeword and a second mode with errors in the parity portion of the codeword.

Abstract: A controller determines, for each read operation, a mathematical model by using a) a set function of a read threshold voltage set among the plurality of read threshold voltages and b) a set checksum value; determines a polynomial regression model based on the mathematical model; determines a parameter set by using multiple computations between input and output matrices based on the polynomial regression model; and estimates a next read threshold voltage for a next read operation based on the parameter set. The controller computes mathematical operation algorithms to replace a normal multiplication operation, a normal division operation and a normal multiplication followed by division operation.

Abstract: Techniques related to improving the error floor performance of a bit flipping (BF) decoder are described. In some examples, error floor performance is improved through determining a set of unreliable check nodes (CNs) and using information about the set of unreliable CNs to compute the flipping energies of variable nodes (VNs). In this manner, the flipping energies can be computed more accurately, thereby lowering the error floor. The set of unreliable CNs can be built through applying various criteria, such as criteria relating to the path length to an unsatisfied CN, the degree of a VN in a path to an unsatisfied CN, and/or checksum value. Path length and VN degree can be applied as selection criteria to determine which CNs qualify as members of the set of unreliable CNs. Checksum value can be applied as a trigger condition for building and/or using the set of unreliable CNs.

Abstract: Devices, systems and methods for improving the performance of a memory device are described. An example method includes performing, based on a plurality of read voltages, read operations on each of a plurality of pages of a memory device, determining, based on the read operations for each page of the plurality of pages, a ones count in each page and a checksum of an error correcting code for each page, generating a first estimator for the checksum and a second estimator for the ones count based on a polynomial regression, determining, based on the first estimator and the second estimator, an updated plurality of read voltages, and applying the updated plurality of read voltages to the memory device to retrieve information from the memory device.

Abstract: Devices, systems and methods for improving the performance of a memory device are described. An example method includes performing, based on a plurality of read voltages, read operations on each of a plurality of pages of a memory device, determining, based on the read operations for each page of the plurality of pages, a ones count in each page and a checksum of an error correcting code for each page, generating a first estimator for the checksum and a second estimator for the ones count based on a polynomial regression, determining, based on the first estimator and the second estimator, an updated plurality of read voltages, and applying the updated plurality of read voltages to the memory device to retrieve information from the memory device.

Abstract: A descrambler receives data from a memory device. The descrambler calculates a sub-syndrome weight for multiple bits in each of the plurality of descrambled sequences using a set parity check matrix to generate multiple sub-syndrome weights, one for each of the plurality of descrambled sequences. The descrambler selects a sub-syndrome weight among the multiple sub-syndrome weights. The descrambler determines, as a correct scrambler sequence for descrambling the data, a scrambler sequence corresponding to the selected sub-syndrome weight, among the plurality of scrambler sequences.

Abstract: A controller optimizes read retry thresholds for a memory device using one or more previous reads and a condition. The controller determines a read level table based on a condition indicative of a state of the memory device and selects an entry among multiple entries in the selected read level table based on a historical read threshold. For the selected entry, the controller: determines fail bits for data associated with multiple read operations on the cells using multiple read retry thresholds; and determines an order of the multiple read retry thresholds based on the fail bits determination.

Abstract: Devices, systems, and methods for detecting and mitigating oscillations in a bit-flipping decoder associated with a non-volatile memory are described. An example method includes receiving a noisy codeword based on a transmitted codeword generated from a low-density parity-check code, performing a first plurality of decoding iterations on the noisy codeword, which comprises performing a message passing algorithm in a first order, computing, based on a completion of the first plurality of decoding iterations, a plurality of checksum values and a plurality of bit flip counts corresponding to the first plurality of decoding iterations, determining that the plurality of checksum values and the plurality of bit flip counts are periodic with a period less than a predetermined threshold, and performing a subsequent decoding iteration on the noisy codeword, the subsequent decoding iteration comprising performing the message passing algorithm in a second order different from the first order.

Abstract: Techniques related to improving power consumption of an LDPC decoder are described. In an example, the LDPC decoder uses a message passing algorithm between variable nodes and check nodes. A check node processing unit that generates check node to variable node messages implements a plurality of check node processing mode. Operation in each mode consumes a certain amount of power while providing a certain accuracy. Depending on a reliability of a variable node to check node message received by the check node processing unit, an appropriate check node processing mode is selected and used to generate a corresponding check node to variable node message. The reliability can be estimated for a set of variable node to check node messages based on, for instance, syndrome-related parameters.

Abstract: A method for capacitance coupling parameter estimation includes determining a plurality of mean voltages among a plurality of memory cells of the memory in each of a plurality of cases related to inter-cell interference, generating a plurality of middle state mean voltages in response to the mean voltages, and adjusting one or more threshold voltages used to read from the memory based on the middle state mean voltages to operate independently of knowledge of middle state distributions in the memory cells.

Abstract: A method is provided for determining log-likelihood ratio (LLR) for soft decoding based on information obtained from hard decoding, in a storage system configured to perform hard decoding and soft decoding of low-density parity-check (LDPC) codewords. The method includes performing hard decoding of codewords in a page, the hard decoding including a first hard read and one or more re-reads using predetermined hard read threshold voltages, and grouping memory cells in the page into a plurality of bins based on the read threshold voltages for the first hard read and the one or more re-reads. The method also includes computing parity checksum and one's count for memory cells in each bin, and determining LLR for each bin of memory cells based on read data, checksums, and one's count for each bin.