Abstract: A method is provided for determining log-likelihood ratio (LLR) for soft decoding based on information obtained from hard decoding, in a storage system configured to perform hard decoding and soft decoding of low-density parity-check (LDPC) codewords. The method includes performing hard decoding of codewords in a page, the hard decoding including a first hard read and one or more re-reads using predetermined hard read threshold voltages, and grouping memory cells in the page into a plurality of bins based on the read threshold voltages for the first hard read and the one or more re-reads. The method also includes computing parity checksum and one's count for memory cells in each bin, and determining LLR for each bin of memory cells based on read data, checksums, and one's count for each bin.

Abstract: Techniques related to improving the decoding performance of codewords, such as LDPC codewords, are described. In an example, the error-correction capability of a decoding layer is improved, where the improvements may include lowering the error floor. To do so, higher order information is used in the decoding. Higher order information refers to, during the decoding of a variable node that is in error, using information that is not limited to the variable node and check nodes connected thereto, but includes information related to variable nodes that are also in error and connected to the variable node via satisfied check nodes and related to unsatisfied check nodes connected to such variable nodes.

Abstract: Devices, systems, and methods for detecting and mitigating oscillations in a bit-flipping decoder associated with a non-volatile memory are described. An example method includes receiving a noisy codeword based on a transmitted codeword generated from a low-density parity-check code, performing a first plurality of decoding iterations on the noisy codeword, which comprises performing a message passing algorithm in a first order, computing, based on a completion of the first plurality of decoding iterations, a plurality of checksum values and a plurality of bit flip counts corresponding to the first plurality of decoding iterations, determining that the plurality of checksum values and the plurality of bit flip counts are periodic with a period less than a predetermined threshold, and performing a subsequent decoding iteration on the noisy codeword, the subsequent decoding iteration comprising performing the message passing algorithm in a second order different from the first order.

Abstract: Memory controllers, decoders and methods to selectively perform bit-flipping (BF) decoding and min-sum (MS) decoding on codewords of an irregular low-density parity-check (LDPC) code. Bit-flipping (BF) decoding is executed with respect to variable nodes having relatively high column weights. MS decoding is executed with respect to variable nodes having relatively low column weights. A column-weight threshold is used to group the variable nodes into the higher and lower column weight groups. The two decoding techniques exchange results during the overall decoding process.

Abstract: Embodiments adaptively determine a read retry threshold voltage for a next read operation using meta information collected from previous failed read data. A controller obtains meta information associated with a read operation on a select page, the meta information including a read threshold voltage set. The controller determines a mathematical model for estimating a checksum value for data associated with a next read operation, using a set function of the read threshold voltage set and a set checksum value. The controller determines a set of parameters by performing polynomial regression on the mathematical model. The controller estimates a next read threshold voltage for the next read operation based on the set of parameters.

Abstract: Embodiments adaptively determine a read retry threshold voltage for a next read operation using meta information collected from previous failed read data. A controller obtains meta information associated with a read operation on a select page, the meta information including a read threshold voltage set. The controller determines a mathematical model for estimating a checksum value for data associated with a next read operation, using a set function of the read threshold voltage set and a set checksum value. The controller determines a set of parameters by performing polynomial regression on the mathematical model. The controller estimates a next read threshold voltage for the next read operation based on the set of parameters.

Abstract: A controller optimizes a read threshold value for a memory device using model-less regression. The controller performs read operations on cells using read threshold voltage values. The controller measures probability values for the multiple read threshold voltage values, and estimates a threshold voltage distribution curve based on the multiple read threshold voltage values and the measured probability values using a set regression formula. The controller determines a read threshold voltage value corresponding to a set point on the threshold voltage distribution curve, and performs a read operation on the cells using the read threshold voltage value.

Abstract: Devices, systems and methods for improving the performance of a memory device are described. An example method includes obtaining a plurality of cell counts for each of a plurality of read voltages applied to the memory device, generating, based on the plurality of cell counts, a set of Gaussian models for a plurality of PV states corresponding to the plurality of read voltages, each of the set of Gaussian models comprising a mean parameter and a standard deviation parameter, determining, based on the set of Gaussian models, the mean parameter and the standard deviation parameter for each of the plurality of PV states, determining, based on the mean parameter and the standard deviation parameter for each of the plurality of PV states, a plurality of updated read voltages, and applying the plurality of updated read voltages to the memory device to retrieve information from the memory device.

Abstract: A controller optimizes a read threshold value for a memory device using model-less regression. The controller performs read operations on cells using read threshold voltage values. The controller measures probability values for the multiple read threshold voltage values, and estimates a threshold voltage distribution curve based on the multiple read threshold voltage values and the measured probability values using a set regression formula. The controller determines a read threshold voltage value corresponding to a set point on the threshold voltage distribution curve, and performs a read operation on the cells using the read threshold voltage value.

Abstract: A controller optimizes read retry thresholds for a memory device using one or more previous reads and a condition. The controller determines a read level table based on a condition indicative of a state of the memory device and selects an entry among multiple entries in the selected read level table based on a historical read threshold. For the selected entry, the controller: determines fail bits for data associated with multiple read operations on the cells using multiple read retry thresholds; and determines an order of the multiple read retry thresholds based on the fail bits determination.

Abstract: Techniques related to improving power consumption of an LDPC decoder are described. In an example, the LDPC decoder uses a message passing algorithm between variable nodes and check nodes. A check node processing unit that generates check node to variable node messages implements a plurality of check node processing mode. Operation in each mode consumes a certain amount of power while providing a certain accuracy. Depending on a reliability of a variable node to check node message received by the check node processing unit, an appropriate check node processing mode is selected and used to generate a corresponding check node to variable node message. The reliability can be estimated for a set of variable node to check node messages based on, for instance, syndrome-related parameters.

Abstract: Memory controllers bit-flipping (BF) decoders and methods that selectively apply a checksum-aided error reduction (CA-ER) scheme to BF decoding of a low-density parity-check (LDPC) code. In decoding a codeword, a hard decision value resulting from decoding a select variable node is changed when a first condition is satisfied to yield an updated hard decision value. Also, when the first condition is satisfied, a current checksum value after processing the select variable node is updated using the updated hard decision value. The CA-ER scheme is applied when the updated checksum value is not reduced to a set minimum and a second condition based on a previous checksum value, calculated after a previous variable node is processed, is satisfied.

Abstract: A controller estimates optimal read threshold values for a memory device using deep learning. The memory device includes multiple pages coupled to select word lines in a memory region. The controller performs multiple read operations on a select type of page for each word line using multiple read threshold sets, obtains fail bit count (FBC) information associated with each read operation, and determines an optimal read threshold set for each word line based on the FBC information. When optimal read threshold sets for the select word lines are different each other, the controller predicts a best read threshold set using the optimal read threshold sets.

Abstract: A controller optimizes read threshold values for a memory device using domain transformation. The controller determines, for the decoded data of each read operation, an asymmetric ratio (AR) and the number of unsatisfied checks (USCs), the AR indicating a ratio of the number of a first binary value to the number of a second binary value in the decoded data. The controller determines a Z-axis such that AR values of the threshold sets are arranged in a set order along the Z-axis. The controller determines an optimum read threshold set using coordinate values on the Z-axis, which correspond to a set AR value and a set USC value.

Abstract: A memory controller optimizes read threshold values for a memory device using multi-dimensional search. The controller performs a read operation on cells using a pair of default read threshold values on a multi-dimensional plane. When the read operation has failed, the controller determines program states of cells and a pair of next read threshold values based on the program states and performs an additional read operation using the next read threshold values.

Abstract: Devices, systems and methods for reducing complexity of a bit-flipping decoder for quasi-cyclic (QC) low-density parity-check (LDPC) codes are described. An example method includes receiving a noisy codeword that is based on a transmitted codeword generated from an irregular QC-LDPC code, the irregular QC-LDPC code having an associated parity matrix, storing, based on a weight of a plurality of columns of the parity matrix of the irregular QC-LDPC code, a portion of the noisy codeword corresponding to the plurality of columns in a first buffer of a plurality of buffers, and accessing and processing the portion of the noisy codeword that includes applying a vertically shuffled scheduling (VSS) scheme that uses a plurality of processing units to determine a candidate version of a portion of the transmitted codeword that corresponds to the portion of the noisy codeword.

Abstract: Multiple memory systems with respective decoders employ a low latency implementation of a read recovery level feature in decoding data. The decoding comprises receiving from a host a read request for decoding read data at a first recovery level by a first memory system, a first decoder of the first memory system being set at a second recovery level with a corresponding maximum iteration number when the read request is received by the first memory system; and operating the first decoder, after a set time elapses, to decode the read data at the second recovery level. A second decoder of a second memory system is set at the first recovery level for at least part of the time during which the first decoder operates to decode the read data at the second recovery level.

Abstract: Devices, systems, and methods for dynamic control of a quasi-cyclic low-density parity-check (QC-LDPC) bit-flipping decoder are described. An example method includes receiving a noisy codeword based on a transmitted codeword generated from an irregular QC-LDPC code, performing a plurality of decoding iterations on the received noisy codeword, each of the plurality of decoding iterations comprising processing of N circulant matrices, performing, before processing a current circulant matrix in a current M-th iteration of the plurality of decoding iterations, operations that include computing a number of bit flips that have occurred over the processing of N previous circulant matrices, the N previous circulant matrices spanning the current M-th iteration and an (M?1)-th iteration, wherein M and N are positive integers, and wherein M?2, and updating, based on the number of bit flips, a bit-flipping threshold, and processing, based on the updated bit-flipping threshold, the current circulant matrix.

Abstract: A descrambler receives data from a memory device. The descrambler calculates a sub-syndrome weight for multiple bits in each of the plurality of descrambled sequences using a set parity check matrix to generate multiple sub-syndrome weights, one for each of the plurality of descrambled sequences. The descrambler selects a sub-syndrome weight among the multiple sub-syndrome weights. The descrambler determines, as a correct scrambler sequence for descrambling the data, a scrambler sequence corresponding to the selected sub-syndrome weight, among the plurality of scrambler sequences.

Abstract: Disclosed are devices, systems and methods for improving a bit-flipping algorithm for an irregular LDPC code in a non-volatile memory device. An example method includes receiving a noisy codeword, the codeword having been generated from an irregular low-density parity-check code, performing a first iteration of a bit-flipping algorithm on the noisy codeword, computing a first syndrome based on an output codeword of the first iteration, determining that the first syndrome comprises a non-zero vector and no bits of the noisy codeword were flipped during the first iteration of the bit-flipping algorithm, flipping, based on the determining, at least one bit of the output codeword, the at least one bit corresponding to a variable node of the plurality of variable nodes with a smallest column weight connected to one or more unsatisfied check nodes of the plurality of check nodes, and computing, subsequent to the flipping, a second syndrome.