Abstract: Embodiments describe a method for reading data from storage that includes selecting a block of memory to read, identifying a read retry table for reading the block, determining that the read retry table for the selected block of memory needs to be updated, and reading the block of memory using a new set of read threshold voltages from the read retry table. Responsive to a successful read operation using the new set of voltages, the method can also include replacing the initial set of read voltages in the first field with the new set of read voltages, and filling the plurality of subsequent fields in the read retry table with additional sets of read threshold voltages identified from a read retry neighbor table, where at least one of the additional sets of read voltages is closest in distance to the initial set of read voltages in read voltage space.

Abstract: Disclosed are devices, systems and methods for improved decoding of a binary linear code. An example method includes receiving a noisy codeword; computing a syndrome based on the noisy codeword; identifying N error patterns that correspond to the syndrome; selecting M error patterns from the N error patterns, wherein M?N are positive integers, wherein a distance between a codeword corresponding to each of the M error patterns and the noisy codeword is less than a distance between a codeword corresponding to any other error pattern and the noisy codeword, and wherein the distance excludes a Hamming distance; modifying the noisy codeword based on each of the M error patterns one-at-a-time; and decoding the modified noisy codeword one-at-a-time until a successful decoding is achieved.

Abstract: An encoder for use in a memory system receives data bits and position information regarding a storage area among storage areas of a memory device in which the data bits are to be stored, determining the number of multiple random sequences to be used based on the position information, scrambling the data bits using the determined number of multiple random sequences, to generate scrambled sequences, selecting from among the generated scrambled sequences the scrambled sequence having the lowest number of a particular logic value, and outputting the selected scrambled sequence for storage in the storage area of the memory device.

Abstract: Memory controllers, decoders and methods to selectively perform bit-flipping (BF) decoding and min-sum (MS) decoding on codewords of an irregular low-density parity-check (LDPC) code. Bit-flipping (BF) decoding is executed with respect to variable nodes having relatively high column weights. MS decoding is executed with respect to variable nodes having relatively low column weights. A column-weight threshold is used to group the variable nodes into the higher and lower column weight groups. The two decoding techniques exchange results during the overall decoding process.

Abstract: Techniques related to improving a performance related to at least data reads from a memory are described. In an example, data is stored in a block of the memory as codewords. A data read includes a determination of whether each bit from a portion of the block is a zero or a one based on voltage measurements. Prior to decoding the codewords by performing a decoding procedure by an ECC decoder of the memory, a first number of errors “E01” and a second number of errors “E10” are estimated, where the first number of errors “E01” is associated with bits each being a true zero and erroneously determined as a one, and where the second number of errors “E10” associated with bits each being a true one and erroneously determined as a zero. Thereafter, the decoding of the codewords based on the decoding procedure is performed.

Abstract: Techniques related to a QoS-aware decoder architecture for data storage are described. In an example, QoS specifications include a QOS latency specification indicative of an acceptable latency for completing the processing of a data read command. The decoder may store this QOS latency specification. In operation, the decoder generates a latency measurement indicative of the actual latency for the processing. If a comparison of the latency measurement and QOS latency specification indicates a violation of the QOS latency specification, the decoder can terminate the decoding and generate a decoding failure.

Abstract: Techniques related to improving a performance related to at least data reads from a memory are described. In an example, a computer system hosts a regression model that includes a neural network. The neural network is trained based on training data that is measured under different combinations of operational conditions and storage conditions. In operation, actual operational and storage conditions associated with the memory are input to the regression model. The neural network outputs a voltage read threshold based on these actual conditions. The computer system uses the voltage read threshold to read data stored in the memory.

Abstract: Techniques related to improving a performance related to at least data reads from a memory are described. In an example, a computer system hosts a regression model that includes a neural network. The neural network is trained based on training data that is measured under different combinations of operational conditions and storage conditions. In operation, actual operational and storage conditions associated with the memory are input to the regression model. The neural network outputs a voltage read threshold based on these actual conditions. The computer system uses the voltage read threshold to read data stored in the memory.

Abstract: A method for capacitance coupling parameter estimation includes determining a plurality of mean voltages among a plurality of memory cells of the memory in each of a plurality of cases related to inter-cell interference, generating a plurality of middle state mean voltages in response to the mean voltages, and adjusting one or more threshold voltages used to read from the memory based on the middle state mean voltages to operate independently of knowledge of middle state distributions in the memory cells.

Abstract: A method for capacitance coupling parameter estimation is disclosed. Step (A) of the method determines a plurality of voltages in a plurality of memory cells of a nonvolatile memory in response to a plurality of writes to the memory cells. The voltages are determined in each of a plurality of cases related to inter-cell interference. Step (B) generates a system of equations of a capacitance coupling model in response to the voltages from all of the cases. Step (C) generates one or more parameters in response to the system of equations. The parameters include one or more couplings between a perturbed memory cell and a plurality of neighboring memory cells adjacent to the perturbed memory cell.

Abstract: A method for determining decision metrics in a detector for a memory device. The method includes receiving a plurality of signal samples and extracting a set of statistics from the signal samples, wherein at least one of the statistics is non-linear or complex, is derived from a plurality of the signal samples, and is not a function of at least one real linear statistic that is derived from a plurality of the signal samples. The method also includes applying at least one decision metric function to the set of statistics to determine at least one decision metric value corresponding to at least one postulated symbol.

Abstract: A method for capacitance coupling parameter estimation is disclosed. Step (A) of the method determines a plurality of voltages in a plurality of memory cells of a nonvolatile memory in response to a plurality of writes to the memory cells. The voltages are determined in each of a plurality of cases related to inter-cell interference. Step (B) generates a system of equations of a capacitance coupling model in response to the voltages from all of the cases. Step (C) generates one or more parameters in response to the system of equations. The parameters include one or more couplings between a perturbed memory cell and a plurality of neighboring memory cells adjacent to the perturbed memory cell.

Abstract: A method for determining decision metrics in a detector for a memory device. The method includes receiving a plurality of signal samples and extracting a set of statistics from the signal samples, wherein at least one of the statistics is non-linear or complex, is derived from a plurality of the signal samples, and is not a function of at least one real linear statistic that is derived from a plurality of the signal samples. The method also includes applying at least one decision metric function to the set of statistics to determine at least one decision metric value corresponding to at least one postulated symbol.