Patents by Inventor Miao Liu
Miao Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20250232720Abstract: A display apparatus is provided. The display apparatus includes a display panel; a memory; and one or more processors. The memory stores computer-executable instructions for controlling the one or more processors to detect a region configured to display a static image; in the region configured to display the static image, detect a parameter of driving transistors of subpixels of a first color in first periods, and detect a parameter of driving transistors of subpixels of a second color in second periods; and determine subpixel values of subpixels in a respective pixel in the static image in a respective frame of image comprising the static image. The parameter of driving transistors of subpixels of the first color is detected with a first frequency; the parameter of driving transistors of subpixels of the second color is detected with a second frequency; and the first frequency is higher than the second frequency.Type: ApplicationFiled: May 24, 2023Publication date: July 17, 2025Applicants: Hefei BOE Joint Technology Co.,Ltd., BOE Technology Group Co., Ltd.Inventors: Huihui Li, Pengfei Yin, Wenchao Bao, Miao Liu, Shuyu Cao
-
Patent number: 12363935Abstract: A semiconductor device includes a substrate, two source/drain features disposed on the substrate, a stack of channel layers disposed over the substrate and between the two source/drain features, and a gate structure disposed over and wrapping around the stack of channel layers. Each channel layer of the stack of channel layers has a dog-bone shape in a cross-sectional view including the two source/drain features and the stack of channel layers. The gate structure includes a seam.Type: GrantFiled: April 29, 2024Date of Patent: July 15, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chang-Miao Liu, Wei-Lun Min
-
Publication number: 20250225907Abstract: A gate driving circuit and a method for driving a gate driving circuit, a display panel, and a display device are provided. The gate driving circuit includes M groups of shift register units, and each group includes one first shift register unit and N?1 second shift register units. The first noise reduction of the first shift register unit performs noise reduction under control of the second node. The second noise reduction circuit of the second shift register units performs noise reduction under control of the second node. In a same group of shift register units, the first shift register unit and the second shift register units share a same second node. A first input signal and a second input signal received by a Kth group of shift register units are a shift signal of a first shift register unit in a (K?2)th group of shift register units.Type: ApplicationFiled: September 30, 2022Publication date: July 10, 2025Inventors: Xiuting LIU, Zhidong YUAN, Can YUAN, Liu WU, Yongqian LI, Cheng XU, Miao LIU, Xing YAO
-
Patent number: 12354544Abstract: A driving circuit, a driving method and a display device are provided. The driving circuit includes a first control node control circuit, a second control node control circuit, a first node control circuit and a second node control circuit, wherein, the first control node control circuit is configured to control a potential of the first control node; the second control node control circuit is configured to control a potential of the second control node; the first node control circuit is configured to control a potential of the first node; the second node control circuit is electrically connected to the second control node, a first clock signal terminal and a second node respectively, and is configured to control to connect the first clock signal terminal and the second node under the control of the potential of the second control node.Type: GrantFiled: November 30, 2022Date of Patent: July 8, 2025Assignee: BOE TECHNOLOGY GROUP CO., LTD.Inventors: Xing Zhang, Pan Xu, Donghui Zhao, Ying Han, Chengyuan Luo, Guangshuang Lv, Cheng Xu, Miao Liu, Dandan Zhou
-
Publication number: 20250208107Abstract: An apparatus for measuring stalk strength of a plant is disclosed. A force sensor is mounted to a harvester in a position to measure the resistance to crushing of the plant stalk by a stalk roll of the harvester. The apparatus may include a pair of counter rotating stalk rolls that pull and crush the plant stalk between them, a force sensor coupled to the stalk rolls for measuring a force exerted on the roller by the plant stalk in resistance to crushing by the stalk roll, and a temperature sensor coupled to the roller for measuring a temperature at or around the force sensor. The output of the force sensor is corrected for temperature-based drifts based on the output of the temperature sensor. Data collected by the invention can be advantageously used in a breeding program wherein breeding decisions are made based at least in part on stalk strength.Type: ApplicationFiled: March 13, 2023Publication date: June 26, 2025Applicant: Syngenta Crop Protection AGInventors: Soumitra Khair, Miao Liu, Scott Tragesser, Joao Oliveira
-
Publication number: 20250203949Abstract: A semiconductor structure includes a substrate including a dielectric layer over a semiconductor layer and an active region protruding from the dielectric layer. The active region includes a stack of semiconductor layers. The semiconductor structure further includes a metal gate structure disposed over the active region and interleaved with the stack of semiconductor layers, an isolation structure over the dielectric layer and covering sidewalls of a bottommost semiconductor layer, and an epitaxial source/drain (S/D) feature disposed adjacent to the metal gate structure. A bottom surface of the epitaxial S/D feature is defined by the bottommost semiconductor layer, and a portion of the bottommost semiconductor layer under the epitaxial S/D feature has a thickness less than a thickness of the dielectric layer.Type: ApplicationFiled: February 17, 2025Publication date: June 19, 2025Inventors: Wei-Lun Min, Ko-Cheng Liu, Chang-Miao Liu
-
Patent number: 12327526Abstract: Disclosed is a drive control circuit including an input circuit (10), a first output circuit (11), and a second output circuit (12). The first output circuit (11) is electrically connected with the input circuit (10) and a first output end (OUT1) and is configured to output a first output signal from the first output end (OUT1) under control of the input circuit (11). The second output circuit (12) is electrically connected with the input circuit (10) and a second output end (OUT2), or electrically connected with the first output end (OUT1) and a second output end (OUT2), and is configured to output a second output signal from the second output end (OUT2) under control of the input circuit (10) or the first output end (OUT1). The first output signal is different from the second output signal.Type: GrantFiled: January 14, 2022Date of Patent: June 10, 2025Assignees: Beijing BOE Technology Development Co., Ltd., BOE Technology Group Co., Ltd.Inventors: Miao Liu, Xing Yao, Yipeng Chen, Teng Chen
-
Patent number: 12324218Abstract: A method includes providing a semiconductor structure including a device fin protruding from a substrate, forming a dummy gate stack over the device fin, forming a first spacer over the device fin and the dummy gate stack, forming a second spacer over the first spacer, forming a dielectric feature adjacent to the second spacer, and replacing the dummy gate stack with a metal gate stack. Thereafter, the method removes the second spacer, thereby forming an air gap between the first spacer and the dielectric feature and wrapping around the device fin. The method then forms a sealing layer over the first spacer and the dielectric feature, thereby sealing the air gap.Type: GrantFiled: July 20, 2021Date of Patent: June 3, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ko-Cheng Liu, Ming-Lung Cheng, Chang-Miao Liu
-
Publication number: 20250176250Abstract: A semiconductor device with different gate structure configurations and a method of fabricating the semiconductor device are disclosed. The method includes depositing a high-K dielectric layer surrounding nanostructured channel regions, performing a first doping with a rare-earth metal (REM)-based dopant on first and second portions of the high-K dielectric layer, and performing a second doping with the REM-based dopants on the first portions of the high-K dielectric layer and third portions of the high-K dielectric layer. The first doping dopes the first and second portions of the high-K dielectric layer with a first REM-based dopant concentration. The second doping dopes the first and third portions of the high-K dielectric layer with a second REM-based dopant concentration different from the first REM-based dopant concentration.Type: ApplicationFiled: January 18, 2025Publication date: May 29, 2025Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Fai CHENG, Chang-Miao LIU, Kuan-Chung CHEN
-
Patent number: 12317550Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a semiconductor stack including semiconductor layers over a substrate, wherein the semiconductor layers are separated from each other and are stacked up along a direction substantially perpendicular to a top surface of the substrate; an isolation structure around a bottom portion of the semiconductor stack and separating active regions; a metal gate structure over a channel region of the semiconductor stack and wrapping each of the semiconductor layers; a gate spacer over a source/drain (S/D) region of the semiconductor stack and along sidewalls of a top portion of the metal gate structure; and an inner spacer over the S/D region of the semiconductor stack and along sidewalls of lower portions of the metal gate structure and wrapping edge portions of each of the semiconductor layers.Type: GrantFiled: August 9, 2023Date of Patent: May 27, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Bwo-Ning Chen, Xusheng Wu, Pin-Ju Liang, Chang-Miao Liu, Shih-Hao Lin
-
Patent number: 12292633Abstract: The present disclosure provides a display device. The display device includes: a display panel including an display area and a peripheral area surrounding the display area; a backlight module at a light incident side of the display panel; where the backlight module includes a backplane, a light guide plate and a plurality of light strips, the backplane includes a first polygonal bottom plate, and a plurality of first side plates connected to the first bottom plate at an edge of the first bottom plate, the light guide plate is located between the first bottom plate and the display panel, and the light strips are located between the first side plates and the light guide plate; and an assembly frame assembled to the display panel and the backlight module at an edge of the display panel and an edge of the backlight module.Type: GrantFiled: May 10, 2022Date of Patent: May 6, 2025Assignees: Beijing BOE Display Technology Co., Ltd., BOE Technology Group Co., Ltd.Inventors: Miao Liu, Huiyan Li, Fuxue Liang, Yu Zhang, Xuefei Qin, Zhuolong Li, Liang Bo, Lulu Wang, Shixin Geng, Fan Yang, Jingrui Ren
-
Publication number: 20250140208Abstract: The display substrate includes a shift register arranged on a base substrate, the shift register includes multiple stages of driving circuits, the driving circuit includes a first/second input circuit, a first/second output circuit and a control circuit; the first output circuit is configured to provide a first scanning driving signal to the first driving signal output terminal under the control of a potential of a first node and a potential of a second node; the first input circuit is configured to input a signal to the third node under the control of the clock signal; the second input circuit is configured to input a signal provided by the power line to the second node under the control of the potential of the third node; the control circuit is configured to control the potential of the third node and the potential of the first node.Type: ApplicationFiled: January 6, 2025Publication date: May 1, 2025Inventors: Miao LIU, Xueguang HAO, Libin LIU, Teng CHEN, Xinyin WU, Yong QIAO, Xing YAO, Jingquan WANG
-
Patent number: 12288516Abstract: A display module includes a display panel, at least one bonding circuit board, a plurality of chip-on-films, and a plurality of buffer devices. The at least one bonding circuit board each include first differential lines, and a first differential line includes a P-polarity differential sub-line and an N-polarity differential sub-line. An end of a chip-on-film is connected to the first differential line, and the other end of the chip-on-film is connected to the display panel. The buffer devices are arranged on the bonding circuit board, a buffer device is connected to ends, proximate to the chip-on-film, of the P-polarity differential sub-line and the N-polarity differential sub-line, and the buffer device is configured to reduce signal reflection between the first differential line and the chip-on-film.Type: GrantFiled: June 24, 2022Date of Patent: April 29, 2025Assignees: Hefei BOE Joint Technology Co., Ltd., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Wenchao Bao, Yue Wu, Huihui Li, Miao Liu, Cheng Xu, Jingbo Xu
-
Patent number: 12288525Abstract: A method of processing data, an electronic device, and a storage medium are provided. The method includes: acquiring voltage values of a plurality of sub-pixels to be detected in the pixel array; determining a plurality of sub-pixels to be compensated from the plurality of sub-pixels to be detected according to the voltage values of the plurality of sub-pixels to be detected, where differences between the voltage values of the plurality of sub-pixels to be compensated and voltage values of corresponding adjacent sub-pixels are greater than or equal to a first filtering threshold; determining at least one sub-pixel column to be compensated according to a position of the plurality of sub-pixels to be compensated in the pixel array; and performing a filtering compensation on the voltage values of a plurality of sub-pixels in the at least one sub-pixel column to be compensated based on a second filtering threshold.Type: GrantFiled: January 16, 2023Date of Patent: April 29, 2025Assignees: Hefei BOE Joint Technology Co., Ltd., BOE Technology Group Co., Ltd.Inventors: Wenchao Bao, Miao Liu, Cheng Xu, Yao Zhang
-
Patent number: 12283248Abstract: The present disclosure provides a circuitry structure and a display substrate. The circuitry structure includes a base substrate, and a functional transistor and a signal transmission line arranged on the base substrate. The functional transistor includes a first conductive connection member, a first electrode, a second electrode, at least two gate electrode patterns and at least one active pattern. Orthogonal projections of the first electrode, the second electrode and the at least two gate electrode patterns onto the base substrate at least partially overlap with an orthogonal projection of the active pattern onto the base substrate, and first ends of the gate electrode patterns are coupled to each other. The first conductive connection member is arranged at a layer different from the gate electrode pattern, and coupled to second ends of the gate electrode patterns. The signal transmission line is coupled to the first conductive connection member.Type: GrantFiled: March 29, 2023Date of Patent: April 22, 2025Assignee: BOE TECHNOLOGY GROUP CO., LTD.Inventors: Chengyuan Luo, Pan Xu, Ying Han, Donghui Zhao, Guangshuang Lv, Xing Zhang, Miao Liu, Xing Yao, Cheng Xu
-
Publication number: 20250124841Abstract: A driving circuit includes a pull-up node control circuit, a pull-down node control circuit and an output circuit; the pull-up node control circuit controls a potential of the pull-up node under the control of an input signal and a reset signal; the output circuit controls the output terminal to output a signal under the control of the potential of the pull-up node and the potential of the pull-down node; a channel length of at least one transistor among at least some transistors included in the output circuit, at least some transistors whose gate electrodes are electrically connected to the input terminal included in the pull-up node control circuit, and at least some transistors whose gate electrodes are electrically connected to the reset terminal included in the pull-up node control circuit is greater than a channel length of another transistor included in the driving circuit.Type: ApplicationFiled: March 31, 2023Publication date: April 17, 2025Inventors: Can YUAN, Yongqian LI, Miao LIU, Dandan ZHOU, Cheng XU
-
Publication number: 20250124876Abstract: The present disclosure provides a circuitry structure and a display substrate. The circuitry structure includes a base substrate, and a functional transistor and a signal transmission line arranged on the base substrate. The functional transistor includes a first conductive connection member, a first electrode, a second electrode, at least two gate electrode patterns and at least one active pattern. Orthogonal projections of the first electrode, the second electrode and the at least two gate electrode patterns onto the base substrate at least partially overlap with an orthogonal projection of the active pattern onto the base substrate, and first ends of the gate electrode patterns are coupled to each other. The first conductive connection member is arranged at a layer different from the gate electrode pattern, and coupled to second ends of the gate electrode patterns. The signal transmission line is coupled to the first conductive connection member.Type: ApplicationFiled: March 29, 2023Publication date: April 17, 2025Applicant: BOE TECHNOLOGY GROUP CO., LTD.Inventors: Chengyuan Luo, Pan Xu, Ying Han, Donghui Zhao, Guangshuang Lv, Xing Zhang, Miao Liu, Xing Yao, Cheng Xu
-
Patent number: 12278276Abstract: Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a diffusion blocking layer on a semiconductor substrate; forming channel material layers over the diffusion blocking layer; patterning the semiconductor substrate, the channel material layers, and the diffusion blocking layer to form a trench in the semiconductor substrate, thereby defining an active region being adjacent the trench; filling the trench with a dielectric material layer and a solid doping source material layer containing a dopant; and driving the dopant from the solid doping source material layer to the active region, thereby forming an anti-punch-through (APT) feature in the active region.Type: GrantFiled: August 30, 2021Date of Patent: April 15, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ko-Cheng Liu, Chang-Miao Liu, Ming-Lung Cheng
-
Publication number: 20250107173Abstract: A method includes providing a substrate, an isolation structure, and a fin extending from the substrate and through the isolation structure. The fin includes a stack of layers having first and second layers that are alternately stacked and have first and second semiconductor materials respectively. A topmost layer of the stack is one of the second layers. The structure further has a sacrificial gate stack engaging a channel region of the fin. The method further includes forming gate spacers and forming sidewall spacers on sidewalls of the fin in a source/drain region of the fin, wherein the sidewall spacers extend above a bottom surface of a topmost one of the first layers. The method further includes etching the fin in the source/drain region, resulting in a source/drain trench; partially recessing the second layers exposed in the source/drain trench, resulting in gaps; and forming dielectric inner spacers inside the gaps.Type: ApplicationFiled: December 9, 2024Publication date: March 27, 2025Inventors: Chun-Fai Cheng, Chang-Miao Liu
-
Patent number: D1080474Type: GrantFiled: July 25, 2023Date of Patent: June 24, 2025Assignee: Nicot Group Co., LtdInventor: Miao Liu