Abstract: A display substrate and a display apparatus. The display substrate includes a display area provided with pixel circuits arranged in an array and a non-display area provided with M light emitting driving circuits, M control driving circuits and M reset driving circuits. Odd-numbered light emitting driving circuits are electrically connected with first and second light emitting clock signal lines, and even-numbered light emitting driving circuits are connected with third and fourth light emitting clock signal lines; and/or, odd-numbered control driving circuits are electrically connected with first and second control clock signal lines, and even-numbered control driving circuits are connected with third and fourth control clock signal lines; and/or, odd-numbered reset driving circuits are electrically connected with first and second reset clock signal lines, and even-numbered reset driving circuits are connected with third and fourth reset clock signal lines.

Abstract: The display panel includes a plurality of pixel units and a sense compensation circuit; and a pixel unit includes a plurality of sub-pixels; a sub-pixel includes a pixel drive circuit and an element to be driven; the display panel further includes: a detection unit and a compensator; the sense compensation circuit is configured to sense the electrical characteristics of said element at a non-active time; the detection unit is configured to detect whether dynamic and static attributes of a picture displayed in a previous preset time period are changed, and send a first notification to the compensator when the dynamic and static attributes are changed; the compensator is configured to receive the first notification and not, according to the sense result of the sense compensation circuit in the previous preset time period, compensate for a picture displayed in a next preset time period.

Abstract: The present disclosure provides semiconductor devices and methods of forming the same. A semiconductor device of the present disclosure includes a first source/drain feature and a second source/drain feature over a substrate, a plurality of channel members extending between the first source/drain feature and the second source/drain feature, a gate structure wrapping around each of the plurality of channel members, and at least one blocking feature. At least one of the plurality of channel members is isolated from the first source/drain feature and the second source/drain feature by the at least one blocking feature.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a first semiconductor fin and a second semiconductor fin formed over a substrate, wherein lower portions of the first semiconductor fin and the second semiconductor fin are separated by an isolation structure; a first gate stack formed over the first semiconductor fin and a second gate stack formed over the second semiconductor fin; and a separation feature separating the first gate stack and the second gate stack, wherein the separation feature includes a first dielectric layer and a second dielectric layer with an air gap defined therebetween, and a bottom portion of the separation feature being inserted into the isolation structure.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a gate stack over the substrate. The semiconductor device structure also includes a spacer element over a sidewall of the gate stack. The spacer element is doped with a dopant, and the dopant contains halide. The spacer element has a first atomic concentration of the dopant near an inner surface of the spacer element adjacent to the gate stack. The spacer element has a second atomic concentration of the dopant near an outer surface of the spacer element. The first atomic concentration of the dopant is different than the second atomic concentration of the dopant.

Abstract: Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a diffusion blocking layer on a semiconductor substrate; forming channel material layers over the diffusion blocking layer; patterning the semiconductor substrate, the channel material layers, and the diffusion blocking layer to form a trench in the semiconductor substrate, thereby defining an active region being adjacent the trench; filling the trench with a dielectric material layer and a solid doping source material layer containing a dopant; and driving the dopant from the solid doping source material layer to the active region, thereby forming an anti-punch-through (APT) feature in the active region.

Abstract: A semiconductor structure includes a substrate, a semiconductor fin-shaped structure protruding from the substrate and extending lengthwise along a first direction, an isolation feature disposed over the substrate and adjacent to the semiconductor fin-shaped structure and extending lengthwise along the first direction, a metal gate stack disposed over a channel region of the semiconductor fin-shaped structure and extending lengthwise along a second direction perpendicular to the first direction, a gate spacer disposed along a sidewall of the metal gate stack and along a sidewall of the semiconductor fin-shaped structure, a source/drain feature disposed over a source/drain region of the semiconductor fin-shaped structure and adjacent to the metal gate stack, a dielectric layer disposed over the source/drain feature, and an air gap disposed between the gate spacer and the dielectric layer along the first direction and wrapping around the semiconductor fin-shaped structure.

Abstract: A semiconductor structure includes a p-type metal-oxide semiconductor (PMOS) region and an n-type metal-oxide semiconductor (NMOS) region, first source/drain (S/D) features in the PMOS region and second S/D features in the NMOS region, a first channel region connecting the first S/D features and a second channel region connecting the second S/D features, a first high-k metal gate stack (HKMG) over the first channel region and a second HKMG over the second channel region, first gate spacers on sidewalls of the first HKMG and second gate spacers on sidewalls of the second HKMG, a first etch-stop layer (ESL) on the first S/D features and the first gate spacers and a second ESL on the second S/D features and the second gate spacers, an oxide layer on the first ESL but not the second ESL, and an interlayer dielectric (ILD) layer on the oxide layer and the second ESL.

Abstract: A semiconductor structure includes a power rail, a dielectric layer over the power rail, a first source/drain feature over the dielectric layer, a via structure extending through the dielectric layer and electrically connecting the first source/drain feature to the power rail, and two dielectric fins disposed on both sides of the first source/drain feature. Each of the dielectric fins includes two seal spacers, a dielectric bottom cover between bottom portions of the seal spacers, a dielectric top cover between top portions of the seal spacers, and an air gap surrounded by the seal spacers, the dielectric bottom cover, and the dielectric top cover.

Abstract: Provided compounds of Formula I and I?, pharmaceutical compositions comprising the compounds, and methods of using the same, in treating, for example, the diseases, disorders, or conditions mediated by the degradation of a protein kinase, such as Hematopoietic progenitor kinase 1 (HPK1).

Abstract: A display substrate, including a scan drive control circuit including an input circuit, an output control circuit, and an output circuit; the input circuit is configured to transmit a signal of the signal input terminal to the output control circuit and a signal of the first clock signal terminal or the first voltage terminal to the output control circuit; the output control circuit is configured to store a signal of the first signal terminal, and transmit a signal of the second signal terminal to the first node; or, the output control circuit is configured to store a signal of the second clock signal terminal, and transmit a signal of the second voltage terminal to the first node; the output circuit is configured to output a signal of the first voltage terminal to the signal output terminal, or output the signal of the second voltage terminal to the signal output terminal.

Abstract: The present disclosure provides compounds of Formula I?, compositions comprising the compound of Formula I?, and methods of using the same, in treating diseases, disorders, or conditions mediated by the inhibition of certain kinases, such as hematopoietic progenitor kinase 1 (HPK1) and/or Fms related receptor tyrosine kinases (FLTs), such as FLT3.

Abstract: The display substrate includes a shift register arranged on a base substrate, and the shift register includes a plurality of stages of driving circuits; a plurality of stages of the driving circuit are provided in the driving circuit area of the base substrate; a stage of driving circuit area includes a first area and a second area, and the first area is provided with a first type of transistor included in the driving circuit, a second type of transistor included in the driving circuit is provided in the second area; one side of the first area is a side of the power line away from the second area, and the other side of the first area is a side close to the second area of an active layer of the first type of transistor close to the second area.

Abstract: Provided are a timing controller, sensing compensation method thereof, and display panel. The timing controller includes a sensing module (501), a built-in picture generation module (502), a multi-channel data selection module (503) and a processing output module (504).

Abstract: A method of processing data, an electronic device, and a storage medium are provided. The method includes: acquiring voltage values of a plurality of sub-pixels to be detected in the pixel array; determining a plurality of sub-pixels to be compensated from the plurality of sub-pixels to be detected according to the voltage values of the plurality of sub-pixels to be detected, where differences between the voltage values of the plurality of sub-pixels to be compensated and voltage values of corresponding adjacent sub-pixels are greater than or equal to a first filtering threshold; determining at least one sub-pixel column to be compensated according to a position of the plurality of sub-pixels to be compensated in the pixel array; and performing a filtering compensation on the voltage values of a plurality of sub-pixels in the at least one sub-pixel column to be compensated based on a second filtering threshold.

Abstract: The present disclosure provides a display device. The display device includes: a display panel including an display area and a peripheral area surrounding the display area; a backlight module at a light incident side of the display panel; where the backlight module includes a backplane, a light guide plate and a plurality of light strips, the backplane includes a first polygonal bottom plate, and a plurality of first side plates connected to the first bottom plate at an edge of the first bottom plate, the light guide plate is located between the first bottom plate and the display panel, and the light strips are located between the first side plates and the light guide plate; and an assembly frame assembled to the display panel and the backlight module at an edge of the display panel and an edge of the backlight module.

Abstract: A method and a system method for real-time wide-field dynamic temperature sensing of an object, the method comprising producing wide-field illumination to upconverting nanoparticles at the object plane, collecting a light emitted by the upconverting nanoparticles, dividing a collected light into a reflected component and a transmitted component, imaging the reflected component into a first image, imaging the transmitted component into a second image; processing the images; and reconstruction of the object from resulting proceed images.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a gate stack over the substrate. The semiconductor device structure also includes a spacer element over a sidewall of the gate stack. The spacer element is doped with a dopant, and the dopant reduces a dielectric constant of the spacer element. The spacer element has a first atomic concentration of the dopant near an inner surface of the spacer element adjacent to the gate stack. The spacer element has a second atomic concentration of the dopant near an outer surface of the spacer element. The first atomic concentration of the dopant is different than the second atomic concentration of the dopant.

Abstract: Field effect transistor and manufacturing method thereof are disclosed. The field effect transistor includes a substrate, fins, a gate structure, a first spacer and a second spacer. The fins protrude from the substrate and extend in a first direction. The gate structure is disposed across and over the fins and extends in a second direction perpendicular to the first direction. The first spacer is disposed on sidewalls of the gate structure. The second spacer is disposed on the first spacer and surrounds the gate structure. The first spacer is fluorine-doped and includes fluorine dopants.