Abstract: A method includes forming a semiconductor substrate having an oxide layer embedded therein, forming a multi-layer (ML) stack including alternating channel layers and non-channel layers over the semiconductor substrate, forming a dummy gate stack over the ML, forming an S/D recess in the ML to expose the oxide layer, forming an epitaxial S/D feature in the S/D recess, removing the non-channel layers from the ML to form openings between the channel layers, where the openings are formed adjacent to the epitaxial S/D feature, and forming a high-k metal gate stack (HKMG) in the openings between the channel layers and in place of the dummy gate stack.

Abstract: A method including providing a device including a gate structure and a source/drain feature adjacent to the gate structure. An insulating layer (e.g., CESL, ILD) is formed over the source/drain feature. A trench is etched in the insulating layer to expose a surface of the source/drain feature. A semiconductor material is then formed in the etched trench on the surface of the source/drain feature. The semiconductor material is converted to a silicide.

Abstract: A semiconductor device structure includes a fin structure formed over a substrate. The structure also includes nanostructures formed over the fin structure. The structure also includes a gate structure wrapped around the nanostructures. The structure also includes a first inner spacer formed beside the gate structure. The structure also includes a second inner spacer formed beside the first inner spacer. The structure also includes spacer layers formed over opposite sides of the gate structure above the nanostructures. The structure also includes source/drain epitaxial structures formed over opposite sides of the fin structure. The second inner spacer is partially embedded in the source/drain epitaxial structures.

Abstract: The present invention provides an optical connector coupled to an optical receptacle, wherein the optical connector comprises an outer housing, a coupling module, and a latch structure. The coupling module is arranged in the outer housing for slidably connecting to the outer housing. When the latch structure is rotated to a first position, the optical connector is unable to be released from the optical receptacle; and when the latch structure is rotated to a second position, the outer housing is allowed to slide relative to coupling module whereby the optical connector is released from the optical receptacle. In one alternative embodiment, the present invention further provides an optical module and an operation method for locking the optical connector into the optical receptacle, or releasing the optical connector from the optical receptacle.

Abstract: Semiconductor devices and methods of forming the same are provided. In an embodiment, an exemplary semiconductor device includes a vertical stack of channel members disposed over a substrate, a gate structure wrapping around each channel member of the vertical stack of channel members, a source/drain feature electrically coupled to the vertical stack of channel members, a silicide layer formed on more than one side of the source/drain feature, and a source/drain contact electrically coupled to the source/drain feature via the silicide layer.

Abstract: A head assembly of optical fiber connector comprises a guiding head, a terminal base, an elastic element, a tube body, and a stopping element. The guiding head has a fiber channel for receiving optical fiber. The terminal base has a front base body and the rear base body, wherein the front base body is utilized for accommodating an end portion of the guiding head. The elastic element is utilized to accommodate with the terminal base. The tube body has an accommodation space for accommodating with the terminal base. The stopping element is arranged into the tube body, and has a through hole allowing the rear base body passing therethrough, wherein a second end of the elastic element is leaned against the stopping element. The present invention further provides a protection cap for protecting the head assembly from being damaged and contaminated.

Abstract: A semiconductor device with different gate structure configurations and a method of fabricating the semiconductor device are disclosed. The method includes depositing a high-K dielectric layer surrounding nanostructured channel regions, performing a first doping with a rare-earth metal (REM)-based dopant on first and second portions of the high-K dielectric layer, and performing a second doping with the REM-based dopants on the first portions of the high-K dielectric layer and third portions of the high-K dielectric layer. The first doping dopes the first and second portions of the high-K dielectric layer with a first REM-based dopant concentration. The second doping dopes the first and third portions of the high-K dielectric layer with a second REM-based dopant concentration different from the first REM-based dopant concentration.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a semiconductor stack including semiconductor layers over a substrate, wherein the semiconductor layers are separated from each other and are stacked up along a direction substantially perpendicular to a top surface of the substrate; an isolation structure around a bottom portion of the semiconductor stack and separating active regions; a metal gate structure over a channel region of the semiconductor stack and wrapping each of the semiconductor layers; a gate spacer over a source/drain (S/D) region of the semiconductor stack and along sidewalls of a top portion of the metal gate structure; and an inner spacer over the S/D region of the semiconductor stack and along sidewalls of lower portions of the metal gate structure and wrapping edge portions of each of the semiconductor layers.

Abstract: The present invention provides an optical-electrical connector and an optical-electrical module thereof, wherein the optical-electrical module comprises the optical-electrical connector and an optical adapter, and the optical-electrical connector comprises an optical connector module, and an electrical connector module slidably coupled to the optical connector module, wherein when the optical-electrical connector is taken away from the an optical adapter by a pulling force, the electrical connector module is unlocked to slide out of the optical adapter earlier than the optical connector module, and the electrical connector module is driven to unlock the optical connector module to release from the optical adapter.

Abstract: A display substrate is provided to include: a base substrate including a display area and a peripheral area surrounding the display area; pixel units in array are in the display area; a driving module is in the peripheral area and is configured to provide electrical signals for the pixel units, to control the pixel units to operate; the driving module includes driving circuits each provided with a corresponding operating signal line group in the peripheral area; the signal line group includes at least two operating signal lines connected to the corresponding driving circuit, to provide electrical signals thereto; the at least two operating signal lines include first and second clock signal lines; the first clock signal lines for at least two driving circuits are a same first clock signal line; and/or the second clock signal lines for the at least two driving circuits are a same second clock signal line.

Abstract: The present disclosure provides a method for calculating an exposure evaluation value and an imaging device. The method includes: dividing an image into a plurality of blocks, the plurality of blocks being arranged in a plurality of rows and columns, for each row of the plurality of rows: for each block of the row: accumulating brightness values of the plurality of pixels in the block to obtain an accumulated brightness value; calculating an average brightness value of the block according to the accumulated brightness value; and writing the average brightness value into a first random access memory, and clearing the plurality of registers in response to writing the average brightness value of each block of the row into the first random access memory, and obtaining an exposure evaluation value according to the average brightness values of the plurality of blocks and predetermined weight coefficients of the plurality of blocks.

Abstract: One or more computer processors compute a maximum likelihood path matrix comprising a respective shortest path between each state in a set of states associated with a model trained with a deep reinforcement learning policy. The one or more computer processors generate explanations for the deep reinforcement learning policy based one or more identified meta-states for each state in the set of states and corresponding selected strategic states utilizing the computed maximum likelihood path matrix.

Abstract: A method including providing a device including a gate structure and a source/drain feature adjacent to the gate structure. An insulating layer (e.g., CESL, ILD) is formed over the source/drain feature. A trench is etched in the insulating layer to expose a surface of the source/drain feature. A semiconductor material is then formed in the etched trench on the surface of the source/drain feature. The semiconductor material is converted to a silicide.

Abstract: A semiconductor device with different gate structure configurations and a method of fabricating the semiconductor device are disclosed. The method includes depositing a high-K dielectric layer surrounding nanostructured channel regions, performing a first doping with a rare-earth metal (REM)-based dopant on first and second portions of the high-K dielectric layer, and performing a second doping with the REM-based dopants on the first portions of the high-K dielectric layer and third portions of the high-K dielectric layer. The first doping dopes the first and second portions of the high-K dielectric layer with a first REM-based dopant concentration. The second doping dopes the first and third portions of the high-K dielectric layer with a second REM-based dopant concentration different from the first REM-based dopant concentration. The method further includes depositing a work function metal layer on the high-K dielectric layer and depositing a metal fill layer on the work function metal layer.

Abstract: A method includes forming a semiconductor fin protruding from a substrate, forming a cladding layer on sidewalls of the semiconductor fin, forming first and second dielectric fins sandwiching the semiconductor fin, and removing the cladding layer. The removal of the cladding layer forms trenches between the semiconductor fin and the first and second dielectric fins. After the removing of the cladding layer, a dummy gate structure is formed over the semiconductor fin and in the trenches. The method also includes recessing the semiconductor fin in a region proximal to the dummy gate structure, forming an epitaxial feature on the recessed semiconductor fin, and forming a metal gate stack replacing the dummy gate structure. A top surface of the recessed semiconductor fin in the region has a concave shape.

Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device of the present disclosure includes a first fin including a first source/drain region, a second fin including a second source/drain region, a first isolation layer disposed between the first source/drain region and the second source/drain region, and a second isolation layer disposed over the first isolation layer. A first portion of the first isolation layer is disposed on sidewalls of the first source/drain region and a second portion of the first isolation layer is disposed on sidewalls of the second source/drain region. A portion of the second isolation layer is disposed between the first portion and second portion of the first isolation layer.

Abstract: A semiconductor structure includes a semiconductor fin protruding from a substrate, a dielectric fin disposed adjacent and substantially parallel to the semiconductor fin, an epitaxial source/drain (S/D) feature disposed in the semiconductor fin, a dielectric layer disposed between a sidewall of the epitaxial S/D feature and a sidewall of the dielectric fin, and an air gap disposed in the dielectric layer.

Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device of the present disclosure includes a first fin including a first source/drain region, a second fin including a second source/drain region, a first isolation layer disposed between the first source/drain region and the second source/drain region, and a second isolation layer disposed over the first isolation layer. A first portion of the first isolation layer is disposed on sidewalls of the first source/drain region and a second portion of the first isolation layer is disposed on sidewalls of the second source/drain region. A portion of the second isolation layer is disposed between the first portion and second portion of the first isolation layer.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a semiconductor stack including semiconductor layers over a substrate, wherein the semiconductor layers are separated from each other and are stacked up along a direction substantially perpendicular to a top surface of the substrate; an isolation structure around a bottom portion of the semiconductor stack and separating active regions; a metal gate structure over a channel region of the semiconductor stack and wrapping each of the semiconductor layers; a gate spacer over a source/drain (S/D) region of the semiconductor stack and along sidewalls of a top portion of the metal gate structure; and an inner spacer over the S/D region of the semiconductor stack and along sidewalls of lower portions of the metal gate structure and wrapping edge portions of each of the semiconductor layers.

Abstract: A semiconductor structure includes a semiconductor fin protruding from a substrate, a dielectric fin disposed adjacent and substantially parallel to the semiconductor fin, an epitaxial source/drain (S/D) feature disposed in the semiconductor fin, a dielectric layer disposed between a sidewall of the epitaxial S/D feature and a sidewall of the dielectric fin, and an air gap disposed in the dielectric layer.