Abstract: A driver circuit for a solid-state relay which includes a split power supply. The positive supply of the split power supply provides a voltage for application to the gate of a power FET for supplying power to a load. The negative supply of the split power supply provides a negative voltage for turning off a control transistor. The control transistor prevents the power FET from conducting power to the load when the driver circuit is turned off. The circuit is particularly adapted for driving a power GaN FET solid state relay. The circuit is provided in a cascaded embodiment to increase the blocking voltage of the solid-state relay.

Abstract: A gate driver circuit which integrates a synchronous bootstrap circuit in an isolation well of an integrated circuit, such that the synchronous bootstrap capacitor connected to the synchronous bootstrap circuit (and to the corresponding switch node of a power converter) can float with the corresponding switch node. Due to this feature, the voltage on one synchronous bootstrapping capacitor can be used to charge the synchronous bootstrapping capacitor of another (higher level) synchronous bootstrap circuit in a separate isolation well connected to a different switch node. As a result, the supply voltages for the synchronous bootstrap circuits in different isolation wells can all be supplied from a single ground referenced supply Vdd.

Abstract: A circuit to enhance the driving capability of conventional inverting bootstrapping GaN drivers. When the inverting driver input is logic high and the driver output is off, the voltage stored on the first bootstrap capacitor for turning on the high side (pull-up) FET of the inverting driver is charged to the full supply voltage using an active charging FET, instead of using a diode or diode-connected FET in a conventional bootstrapping driver. The gate voltage of the active charging FET is bootstrapped to a voltage higher than supply voltage by a second bootstrap capacitor that connects to the inverting driver input, which is at a logic high. The second bootstrap capacitor is charged by an additional diode or diode-connected FET connected to the supply voltage when the inverting driver input is a logic low.

Abstract: A multi-level converter includes a flying capacitor and a resistive voltage divider. The multi-level converter is configured to convert an input voltage into an output voltage. The resistive voltage divider is configured to charge a flying capacitor in the multi-level converter during an initial charging mode of operation. In some implementations, the multi-level converter includes a plurality of flying capacitors and a plurality of resistive voltage dividers including a resistive voltage divider for each flying capacitor in the plurality of flying capacitors.

Abstract: A physical arrangement of at least two power switches and at least one capacitor in a power loop. At least one of the switches is formed of at least two parallel electronic devices, such as transistors. The arrangement minimizes total power loop impedance and results in approximately equal impedance in each parallel branch of the switch formed of two parallel devices, thereby resulting in approximately equal currents in the switches.

Abstract: An enhancement mode GaN FET based gate driver circuit including an active pre-driver to drive a high-slew rate, high current output stage GaN FET. Due to the active driver current from the pre-driver, the output stage pull-up FET can turn on faster as compared to a pre-driver that utilizes a passive pull-up load. The active pre-driver must provide a voltage to drive the gate of the output stage pull-up FET which is higher than the normal supply voltage to enable the maximum output level of the driver FET to approach the normal supply voltage. A feedback circuit is included in the active pre-driver to avoid the need for two supply voltages.

Abstract: A highly efficient, multi-layered, single component sided circuit board layout design providing reduced parasitic inductance for power switched circuits. Mounted on the top board are one or more transistor switches, one or more loads, and one or more capacitors. The switches and capacitors form a loop with very low parasitic inductance. The loads may be a part of the loop, i.e. in series with the switches and capacitors, or may be connected to two or more nodes of the loop to form additional loops with common vertices. Parallel wide conductors carry the switch load current resulting in a low inductance path for the power loop. The power loop and gate loop current travel in opposite directions and are well separated, minimizing common source inductance (CSI) and maximizing switching speed.

Abstract: A multi-level converter includes a flying capacitor and a resistive voltage divider. The multi-level converter is configured to convert an input voltage into an output voltage. The resistive voltage divider is configured to charge a flying capacitor in the multi-level converter during an initial charging mode of operation. In some implementations, the multi-level converter includes a plurality of flying capacitors and a plurality of resistive voltage dividers including a resistive voltage divider for each flying capacitor in the plurality of flying capacitors.

Abstract: A common gate amplifier circuit configured to provide decreased voltage transients in the input voltage due to reverse gain. A second FET transistor is connected in series with a first FET of the common gate amplifier to function as an additional capacitive voltage divider between the amplifier output and the amplifier input without influencing the input or output currents. The first FET transistor, coupled to the amplifier input, may be a low voltage FET and smaller than the second FET transistor, which is coupled to the amplifier output. Both FET transistors are preferably enhancement mode GaN FET transistors and may be integrated into a single semiconductor chip with a single internal bias voltage divider.

Abstract: A current measurement circuit for determining a start time tSTART, an end time tEND, and/or a peak time tMAX for a current pulse passing through a current conductor. The current measurement circuit includes a pickup coil and a threshold crossing detector. The pickup coil generates a voltage VSENSE? proportional to a magnetic field around the conductor, which is proportional to a change in current over time. The threshold crossing detector compares VSENSE? and a threshold voltage and generates an output signal indicative of a transition time and whether a slope of VSENSE? is positive or negative. The current measurement circuit can also include an integrator and a sample and hold circuit. The integrator integrates VSENSE? over time and generates an integrated signal VSENSE. The sample and hold circuit compares VSENSE to tMAX and generates a second output signal which can be used to measure the pulse current.

Abstract: A large area wireless power system having a synchronization transmitter and a plurality of synchronization receivers for receiving a plurality of differential signals from the synchronization transmitter and outputting a plurality of second single-ended signals. The synchronization transmitter generates a first single-ended signal and converts the first single-ended signal into the plurality of differential signals to be transmitted to the synchronization receivers over a plurality of differential line pairs that also provide power to the synchronization receivers. The large area wireless power system also includes a plurality of high power amplifiers for receiving the plurality of second single-ended signals from the respective synchronization receivers and generating power, and a plurality of wireless power coils for receiving the power generated by the plurality of high power amplifiers and wirelessly providing power.

Abstract: A scalable highly resonant wireless power coil structure that is suitable for use across a large surface area. The structure includes a plurality of single turn loops with adjacent loops that are decoupled from each other, yet form part of a single member.

Abstract: A highly efficient, multi-layered, single component sided circuit board layout design providing reduced parasitic inductance for power switched circuits. Mounted on the top board are one or more transistor switches, one or more loads, and one or more capacitors. The switches and capacitors form a loop with very low parasitic inductance. The loads may be a part of the loop, i.e. in series with the switches and capacitors, or may be connected to two or more nodes of the loop to form additional loops with common vertices. Parallel wide conductors carry the switch load current resulting in a low inductance path for the power loop. The power loop and gate loop current travel in opposite directions and are well separated, minimizing common source inductance (CSI) and maximizing switching speed.

Abstract: A wireless power receiver circuit includes an active rectifier circuit with a plurality of power transistors, wherein the active rectifier circuit is configured to rectify an induced AC receiver current. The wireless power receiver circuit includes also includes a gate drive controller circuit configured to sense the induced AC receiver current and to provide gate drive signals for the plurality of power transistors synchronized with the induced AC receiver current. The gate drive controller circuit includes a current sense circuit configured to provide two voltage signals having a difference proportional to the induced AC receiver current.

Abstract: A cascaded bootstrapping gate driver configured to provide quick turn-on of a high side power FET and low static current consumption. The cascaded bootstrapping gate driver includes an initial bootstrapping stage with a resistor to decrease static current consumption during transistor turn-off. A secondary bootstrapping stage is driven by the initial bootstrapping stage and includes a GaN FET transistor with a low on resistance in place of the resistor. The source terminal of the GaN FET transistor provides a gate driving voltage to the high side power switch FET. The low on-resistance of the GaN FET transistor provides quick turn-on of the high side power FET. Transistors in the cascaded bootstrapping gate driver are preferably enhancement mode GaN FETs and may be integrated into a single semiconductor die.

Abstract: A power converter in which two power FETs are provided in a full bridge arrangement with two diodes for supplying a rectified voltage to a load. The gates of the power FETs receive alternating and opposite voltage waveforms such that the power FETs conduct oppositely to each other. A turn-off FET is connected to the gate of each power FET to prevent spurious turn on of the power FET during periods in which the opposite power FET is turned on. A voltage sense FET is also connected to the gate of each power FET to limit the gate voltage of the power FET. The voltage sense FETs are each synchronously modulated with the corresponding power FET to limit the gate to source voltage of the voltage sense FET when the corresponding turn-off FET is on and the corresponding power FET is off.

Abstract: A current measurement circuit for determining a start time tSTART, an end time tEND, and/or a peak time tMAX for a current pulse passing through a current conductor. The current measurement circuit comprises a pickup coil and a threshold crossing detector. The pickup coil generates a voltage VSENSE? proportional to a magnetic field around the conductor, which is proportional to a change in current over time. The threshold crossing detector compares VSENSE? and a threshold voltage and generates an output signal indicative of a transition time and whether a slope of VSENSE? is positive or negative. The current measurement circuit can also comprise an integrator and a sample and hold circuit. The integrator integrates VSENSE? over time and generates an integrated signal VSENSE. The sample and hold circuit compares VSENSE to tMAX and generates a second output signal which can be used to measure the pulse current.

Abstract: A cascaded synchronous bootstrap supply circuit with reduced voltage drop between the cascaded bootstrap capacitors by replacing bootstrap diodes with gallium nitride (GaN) transistors. GaN transistors have a much lower forward voltage drop than diodes, thus providing a cascaded gate driver bootstrap supply circuit with a reduced drop in bootstrap capacitor voltage, which is particularly important as the number of levels increases.

Abstract: A cascaded bootstrapping gate driver configured to provide quick turn-on of a high side power FET and low static current consumption. The cascaded bootstrapping gate driver includes an initial bootstrapping stage with a resistor to decrease static current consumption during transistor turn-off. A secondary bootstrapping stage is driven by the initial bootstrapping stage and includes a GaN FET transistor with a low on resistance in place of the resistor. The source terminal of the GaN FET transistor provides a gate driving voltage to the high side power switch FET. The low on-resistance of the GaN FET transistor provides quick turn-on of the high side power FET. Transistors in the cascaded bootstrapping gate driver are preferably enhancement mode GaN FETs and may be integrated into a single semiconductor die.

Abstract: A common gate amplifier circuit configured to provide decreased voltage transients in the input voltage due to reverse gain. A second FET transistor is connected in series with a first FET of the common gate amplifier to function as an additional capacitive voltage divider between the amplifier output and the amplifier input without influencing the input or output currents. The first FET transistor, coupled to the amplifier input, may be a low voltage FET and smaller than the second FET transistor, which is coupled to the amplifier output. Both FET transistors are preferably enhancement mode GaN FET transistors and may be integrated into a single semiconductor chip with a single internal bias voltage divider.