Abstract: A power factor correction (PFC) boost circuit. The PFC boost circuit can include a first switching device, a second switching device, a first gate driver coupled to the first switching device, a second gate driver coupled to the second switching device, and a PFC controller configured to control the first and second gate drivers. The PFC controller will utilize a new technique, referred to herein as “predictive diode emulation” to control the switching devices in a desired manner and to overcome inefficiencies and other problems that might arise using traditional diode emulation. The PFC controller is configured to operate in synchronous and non-synchronous modes.

Abstract: A circuit and technique are provided to control bias setting to an FET based common source RF amplifier that can operate with large signals present. The circuit and technique described herein use a second FET in an identical circuit having the gate circuits connected in parallel and being sourced by the same drain voltage that serves as a reference to a first circuit bias setting. The drain current in a first FET will include both the bias and RF amplification current, whereas the second FET only carries the bias current. Because the devices and circuits are matched, the gate voltage variations will appear in both FETs thereby providing regulation of the drain current.

Abstract: Parallel transistor circuits with reduced effects from common source induction. The parallel transistors include physical gate connections that are located electrically close to one another. The parallel circuits are arranged such that the voltage at the common gate connection resulting from transient currents across common source inductance is substantially balanced. The circuits include switching circuits, converters, and RF amplifiers.

Abstract: An electrical circuit arranged in a half bridge topology. The electrical circuit includes a high side transistor; a low side transistor; a gate driver and level shifter electrically coupled to a gate of the high side transistor; a gate driver electrically coupled to a gate of the low side transistor; a capacitor electrically coupled in parallel with the gate driver and level shifter; a voltage source electrically coupled to an input of the gate driver and level shifter and an input of the gate driver; and, a bootstrap transistor electrically coupled between the voltage source and the capacitor. A GaN field-effect transistor is synchronously switched with a low side device of the half bridge circuit.

Abstract: A GaN transistor with polysilicon layers for creating additional components for an integrated circuit and a method for manufacturing the same. The GaN device includes an EPI structure and an insulating material disposed over EPI structure. Furthermore, one or more polysilicon layers are disposed in the insulating material with the polysilicon layers having one or more n-type regions and p-type regions. The device further includes metal interconnects disposed on the insulating material and vias disposed in the insulating material layer that connect source and drain metals to the n-type and p-type regions of the polysilicon layer.

Abstract: A high efficiency voltage mode class D amplifier and energy transfer system is provided. The amplifier and system includes a pair of transistors connected in series between a voltage source and a ground connection. Further, a ramp current tank circuit is coupled in parallel with one of the pair of transistors and a resonant tuned load circuit is coupled to the ramp current tank circuit. The ramp current tank circuit can include an inductor that absorbs an output capacitance COSS of the pair of transistors and a capacitor the provides DC blocking.

Abstract: A circuit and technique are provided to control bias setting to an FET based common source RF amplifier that can operate with large signals present. The circuit and technique described herein use a second FET in an identical circuit having the gate circuits connected in parallel and being sourced by the same drain voltage that serves as a reference to a first circuit bias setting. The drain current in a first FET will include both the bias and RF amplification current, whereas the second FET only carries the bias current. Because the devices and circuits are matched, the gate voltage variations will appear in both FETs thereby providing regulation of the drain current.

Abstract: A power factor correction (PFC) boost circuit. The PFC boost circuit can include a first switching device, a second switching device, a first gate driver coupled to the first switching device, a second gate driver coupled to the second switching device, and a PFC controller configured to control the first and second gate drivers. The PFC controller will utilize a new technique, referred to herein as “predictive diode emulation” to control the switching devices in a desired manner and to overcome inefficiencies and other problems that might arise using traditional diode emulation. The PFC controller is configured to operate in synchronous and non-synchronous modes.

Abstract: Parallel transistor circuits with reduced effects from common source induction. The parallel transistors include physical gate connections that are located electrically close to one another. The parallel circuits are arranged such that the voltage at the common gate connection resulting from transient currents across common source inductance is substantially balanced. The circuits include switching circuits, converters, and RF amplifiers.

Abstract: An inductor includes an electrical conductor wound in a magnetic flux concentrating pattern, the electrical conductor comprises a plurality of carbon nanotubes that are substantially aligned with an axis along a center of the electrical conductor.

Abstract: A balun is included in a magnetic resonance imaging system. The balun conditions electromagnetic signals received from at least one RF receiver coil. The balun includes a balun shield having an integrated capacitor therein. The balun blocks unwanted feedback from effecting performance of any components contained within the balun shield.

Abstract: An integrated balun-low noise amplifier (LNA) system is included in a magnetic resonance imaging system. The integrated balun-LNA system conditions electromagnetic signals received from at least one RF receiver coil. The integrated balun-LNA system is configured to be enclosed in a balun housing. The size of the integrated balun-LNA system minimizes component area and volume thereof on or near the RF receiver coil and thus, minimizes interference with the magnetic flux field.

Abstract: A balun is included in a magnetic resonance imaging system. The balun conditions electromagnetic signals received from at least one RF receiver coil. The balun includes a balun shield having an integrated capacitor therein. The balun shield blocks unwanted feedback from effecting performance of any components contained within the balun shield.

Abstract: An inductor includes an electrical conductor wound in a magnetic flux concentrating pattern, the electrical conductor comprises a plurality of carbon nanotubes that are substantially aligned with an axis along a center of the electrical conductor.

Abstract: An integrated balun-low noise amplifier (LNA) system is included in a magnetic resonance imaging system. The integrated balun-LNA system conditions electromagnetic signals received from at least one RF receiver coil. The integrated balun-LNA system is configured to be enclosed in a balun housing. The size of the integrated balun-LNA system minimizes component area and volume thereof on or near the RF receiver coil and thus, minimizes interference with the magnetic flux field.

Abstract: A power module includes a substrate that includes an upper layer, an electrical insulator and a thermal coupling layer. The upper layer includes an electrically conductive pattern and is configured for receiving power devices. The electrical insulator is disposed between the upper layer and the thermal coupling layer. The thermal coupling layer is configured for thermal coupling to a heat sink. The power module further includes at least one laminar interconnect that includes first and second electrically conductive layers and an insulating layer disposed between the first and second electrically conductive layers. The first electrically conductive layer of the laminar interconnect is electrically connected to the upper layer of the substrate. Electrical connections connect a top side of the power devices to the second electrically conductive layer of the laminar interconnect.

Abstract: A dual coil induction cooking system and method for heating ferrous and non-ferrous cooking vessels. The system includes a first resonant circuit for inducing a current in a ferrous metal cooking vessel at a first frequency and a second resonant circuit, wired in a parallel combination with the first resonant circuit, for inducing a current in a non-ferrous metal cooking vessel at a second frequency. The system also includes a power source for powering the parallel combination, so that one of the first and the second resonant circuits is coupled to supply power through the parallel combination to a respective one of the cooking vessels. A method for coupling power to a load includes sweeping a parallel combination of resonant circuits with a variable frequency power, detecting a resonant frequency response corresponding to a metallic composition of the load, and simultaneously powering the parallel combination of resonant circuits at a frequency corresponding to the detected resonant frequency.

Abstract: A power module includes a substrate that includes an upper layer, an electrical insulator and a thermal coupling layer. The upper layer includes an electrically conductive pattern and is configured for receiving power devices. The electrical insulator is disposed between the upper layer and the thermal coupling layer. The thermal coupling layer is configured for thermal coupling to a heat sink. The power module further includes at least one laminar interconnect that includes first and second electrically conductive layers and an insulating layer disposed between the first and second electrically conductive layers. The first electrically conductive layer of the laminar interconnect is electrically connected to the upper layer of the substrate. Electrical connections connect a top side of the power devices to the second electrically conductive layer of the laminar interconnect.

Abstract: An AC ripple current reduction circuit for an AC converter having: an AC voltage source at the input; a first capacitor across which the circuit output voltage is provided; a first, main inductor in series with the first capacitor and the input; an auxiliary circuit including a second capacitor and a transformer coupled to the main inductor, the secondary of the transformer being in series with the second capacitor; and a means for enabling the flow of a time varying voltage across the first and second capacitors that has a frequency much less than the ripple frequency of the current in the main inductor.

Abstract: A dual coil induction cooking system and method for heating ferrous and non-ferrous cooking vessels. The system includes a first resonant circuit for inducing a current in a ferrous metal cooking vessel at a first frequency and a second resonant circuit, wired in a parallel combination with the first resonant circuit, for inducing a current in a non-ferrous metal cooking vessel at a second frequency. The system also includes a power source for powering the parallel combination, so that one of the first and the second resonant circuits is coupled to supply power through the parallel combination to a respective one of the cooking vessels. A method for coupling power to a load includes sweeping a parallel combination of resonant circuits with a variable frequency power, detecting a resonant frequency response corresponding to a metallic composition of the load, and simultaneously powering the parallel combination of resonant circuits at a frequency corresponding to the detected resonant frequency.