Patents by Inventor Michael A. Gaynes
Michael A. Gaynes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6427323Abstract: A method is provided for connecting two conductive layers in an electronic circuit package comprising the steps of forming dendrites on selected regions of a first conductive layer, forming dendrites on selected regions of a second conductive layer, applying an epoxy adhesive material over the first conductive layer, and compressively attaching the second conductive layer to the first conductive layer such that the dendrites on the first conductive layer contact the dendrites on the second conductive layer. Also claimed is an electronic circuit package incorporating the dendrites used for electrical interconnection manufactured in accordance with the present invention. An alternative embodiment of the invention utilizes an intermediate surface metal with dendrites in place of a “through via.Type: GrantFiled: May 17, 2001Date of Patent: August 6, 2002Assignee: International Business Machines CorporationInventors: Bernd K. Appelt, Saswati Datta, Michael A. Gaynes, John M. Lauffer, James R. Wilcox
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Publication number: 20020079048Abstract: A method and resulting electronic package in which a heat sink is secured to the package's dielectric material (e.g., overmold). The surface of the dielectric is roughened (e.g., using an abrasive paper or pad) to enhance the subsequent dielectric-heat sink bond in which an adhesive is used. The dielectric material's roughened external surface(s), typically containing silicone material (e.g., silicone residue) which is an inherent by-product of many dielectric materials of the type used in such packaging, is (are) able to still be securely attached to the heat sink, despite the presence of said silicone. In another embodiment, the roughened surface enhances the marking of dielectric material of this type (e.g., using ink).Type: ApplicationFiled: February 28, 2002Publication date: June 27, 2002Applicant: International Business Machines CorporationInventors: Michael Gaynes, William R. Hill
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Patent number: 6410988Abstract: A method of making a flip chip package that maintains flatness over a wide temperature range and provides good heat dissipation is described. A laminate substrate is electrically connected to electrical contacts disposed on a chip and underfill material is applied between the soldered connections. A body, for example an uncured dielectric material, is applied to the chip, the laminate substrate, a thermally conductive member or combinations thereof, and thermally conductive member is disposed adjacent to the surface of the chip that is opposite the surface connected to the laminate substrate. The body is extruded between the chip and the thermally conductive member. The thickness of the thermally conductive member is determined by balancing the stiffness and the CTE of both the thermally conductive member and the laminate substrate, and the length and width of the thermally conductive member may vary but are at least the size of the corresponding length and width of the chip.Type: GrantFiled: May 15, 2000Date of Patent: June 25, 2002Assignee: International Business Machines CorporationInventors: David V. Caletka, Jean Dery, Eric Duchesne, Michael A. Gaynes, Eric A. Johnson, Luis J. Matienzo, James R. Wilcox
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Publication number: 20020046804Abstract: A semiconductor chip carrier assembly which includes a flexible substrate having a metallicized path on one of its surfaces in electrical communication with a semiconductor chip. A stiffener is disposed adjacent to said flexible substrate and is bonded thereto by an adhesive composition. The adhesive composition which comprises a microporous film laden with a curable adhesive is disposed between the flexible substrate and the stiffener. A cover plate is adhesively bonded to the semiconductor chip and to the stiffener. A process of making the assembly involving disposition of the flexible substrate in a vacuum fixture upon which the adhesive composition and stiffener is placed followed by the application of heat and pressure to cure the curable adhesive is also described.Type: ApplicationFiled: September 16, 1999Publication date: April 25, 2002Inventors: THOMAS M. CULNANE, MICHAEL A. GAYNES, RAMESH R. KODNANI, MARK V. PIERSON, CHARLES G. WOYCHIK
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Patent number: 6369452Abstract: An electronic structure bondable to an electronic assembly, such as a chip. The electronic structure may be joined to a electronic assembly, such as a chip, by use of a structural epoxy adhesive. The electronic structure includes a mineral layer on a metallic plate, and an adhesion promoter layer on the mineral layer. The metallic plate includes a metallic substance that includes a pure metal with or without a metal coating. The metallic substance may include such substances as stainless steel, aluminum, titanium, copper, copper coated with nickel, and copper coated with chrome. The mineral layer includes a chemical compound derived from a mineral; e.g., silicon dioxide (SiO2) derived from quartz. Such chemical compounds may include such substances as silicon dioxide, silicon nitride, and silicon carbide. The chemical compound may exist in either crystalline or amorphous form. The adhesion promoter may include such chemical substances as silanes, titanates, zirconates, and aluminates.Type: GrantFiled: July 27, 1999Date of Patent: April 9, 2002Assignee: International Business Machines CorporationInventors: Stephen Leslie Buchwalter, Hung Manh Dang, Michael A. Gaynes, Konstantinos I. Papathomas
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Patent number: 6344099Abstract: A system for aligning and attaching together a plurality of thin film transistor tiles for constructing a flat panel display. A coverplate loading station where a coverplate that the tiles are to be attached to is arranged on a coverplate support. A coverplate bonding material dispensing station where a bonding material for bonding the tiles to the coverplate is applied to a surface of the coverplate. A tile placement station where the tiles are arranged on the coverplate. A tile aligning and securing station where the tiles are aligned relative to each other and the coverplate by the tile aligner and where the tiles are at least partially bonded to the coverplate. A tile assembly bonding material dispensing station where a bonding material is applied to a surface of the tiles opposite the side that the coverplate is bonded to. A backplate placement station where a backplate is arranged on the tiles.Type: GrantFiled: September 25, 2000Date of Patent: February 5, 2002Assignee: International Business Machines CorporationInventors: Michael A. Gaynes, Allan O. Johnson, Ramesh R. Kodnani, Mark V. Pierson, Edward J. Tasillo
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Publication number: 20020005245Abstract: A method for bonding heat sinks to packaged electronic components comprises the steps of: (a) exposing to a plasma a surface of a molded polymer formed on a substrate; (b) allowing the plasma to at least partially convert silicon-containing residue on the surface to silica; and (c) bonding an article to the surface by applying an adherent between the article and the surface. Often, the silicon-containing residue is silicone oil, a mold release compound, which may prevent the formation of a bond when using conventional bonding methods and materials. The silica layer formed on the surface of the molded polymer assists in formation of a proper bond. The plasma may be an oxygen plasma and the adherent may be selected from either a heat cured silicone-based paste adhesive with a metal oxide filler or a heat cured porous polymer film impregnated with adhesive.Type: ApplicationFiled: January 9, 2001Publication date: January 17, 2002Inventors: Frank D. Egitto, Michael A. Gaynes, Ramesh R. Kodnani, Luis J. Matienzo, Mark V. Pierson
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Publication number: 20010034937Abstract: A method is provided for connecting two conductive layers in an electronic circuit package comprising the steps of forming dendrites on selected regions of a first conductive layer, forming dendrites on selected regions of a second conductive layer, applying an epoxy adhesive material over the first conductive layer, and compressively attaching the second conductive layer to the first conductive layer such that the dendrites on the first conductive layer contact the dendrites on the second conductive layer. Also claimed is an electronic circuit package incorporating the dendrites used for electrical interconnection manufactured in accordance with the present invention. An alternative embodiment of the invention utilizes an intermediate surface metal with dendrites in place of a “through via.Type: ApplicationFiled: May 17, 2001Publication date: November 1, 2001Applicant: International Business Machines CorporationInventors: Bernd K. Appelt, Saswati Datta, Michael A. Gaynes, John M. Lauffer, James R. Wilcox
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Publication number: 20010035759Abstract: A method and device for testing and burning-in semiconductor circuits. The method and device permit the entire wafer to be tested by temporarily attaching the wafer to a test substrate using electrically conductive adhesive (ECA). The ECA conforms to deviations from co-planarity of the contact points of both the wafer and test substrate while providing a quality electrical connection at each point. ECA material can be deposited on either the wafer contacts or the substrate pads. In addition, the ECA may be deposited on C4 bumps or tin-capped lead bases. Variations in the method and device include filling vias of a non-conductive interposer with ECA. The electrical connection may be enhanced by forming conductive dendrites on test pads while the ECA is deposited on the wafer contacts. To further enhance the electrical connection, the ECA material can be plasma etched to remove some of its polymer matrix and to expose the electrically conductive particles on one side and then plating with palladium.Type: ApplicationFiled: June 6, 2001Publication date: November 1, 2001Inventors: William E. Bernier, Michael A. Gaynes, Wayne J. Howell, Mark V. Pierson, Ajit K. Trivedi, Charles G. Woychik
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Patent number: 6300575Abstract: A method is provided for connecting two conductive layers in an electronic circuit package comprising the steps of forming dendrites on selected regions of a first conductive layer, forming dendrites on selected regions of a second conductive layer, applying an epoxy adhesive material over the first conductive layer, and compressively attaching the second conductive layer to the first conductive layer such that the dendrites on the first conductive layer contact the dendrites on the second conductive layer. Also claimed is an electronic circuit package incorporating the dendrites used for electrical interconnection manufactured in accordance with the present invention. An alternative embodiment of the invention utilizes an intermediate surface metal with dendrites in place of a “through via.Type: GrantFiled: August 25, 1997Date of Patent: October 9, 2001Assignee: International Business Machines CorporationInventors: Bernd K. Appelt, Saswati Datta, Michael A. Gaynes, John M. Lauffer, James R. Wilcox
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Publication number: 20010024127Abstract: A method and device for testing and burning-in semiconductor circuits. The method and device permit the entire wafer to be tested by temporarily attaching the wafer to a test substrate using electrically conductive adhesive (ECA). The ECA conforms to deviations from co-planarity of the contact points of both the wafer and test substrate while providing a quality electrical connection at each point. ECA material can be deposited on either the wafer contacts or the substrate pads. In addition, the ECA may be deposited on C4 bumps or tin-capped lead bases. Variations in the method and device include filling vias of a non-conductive interposer with ECA. The electrical connection may be enhanced by forming conductive dendrites on test pads while the ECA is deposited on the wafer contacts. To further enhance the electrical connection, the ECA material can be plasma etched to remove some of its polymer matrix and to expose the electrically conductive particles on one side and then plating with palladium.Type: ApplicationFiled: March 30, 1998Publication date: September 27, 2001Inventors: WILLIAM E. BERNIER, MICHAEL A. GAYNES, WAYNE J. HOWELL, MARK V. PIERSON, AJIT K. TRIVEDI, CHARLES G. WOYCHIK
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Patent number: 6288559Abstract: A method and device for testing and burning-in semiconductor circuits. The method and device permit the entire wafer to be tested by temporarily attaching the wafer to a test substrate using electrically conductive adhesive (ECA). The ECA conforms to deviations from co-planarity of the contact points of both the wafer and test substrate while providing a quality electrical connection at each point. ECA material can be deposited on either the wafer contacts or the substrate pads. In addition, the ECA may be deposited on C4 bumps or tin-capped lead bases. Variations in the method and device include filling vias of a non-conductive interposer with ECA. The electrical connection may be enhanced by forming conductive dendrites on test pads while the ECA is deposited on the wafer contacts. To further enhance the electrical connection, the ECA material can be plasma etched to remove some of its polymer matrix and to expose the electrically conductive particles on one side and then plating with palladium.Type: GrantFiled: March 30, 1998Date of Patent: September 11, 2001Assignee: International Business Machines CorporationInventors: William E. Bernier, Michael A. Gaynes, Wayne J. Howell, Mark V. Pierson, Ajit K. Trivedi, Charles G. Woychik
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Patent number: 6268739Abstract: A method and device for testing and burning-in semiconductor circuits. The method and device permit the entire wafer to be tested by temporarily attaching the wafer to a test substrate using electrically conductive adhesive (ECA). The ECA conforms to deviations from co-planarity of the contact points of both the wafer and test substrate while providing a quality electrical connection at each point. ECA material can be deposited on either the wafer contacts or the substrate pads. In addition, the ECA may be deposited on C4 bumps or tin-capped lead bases. Variations in the method and device include filling vias of a non-conductive interposer with ECA. The electrical connection may be enhanced by forming conductive dendrites on test pads while the ECA is deposited on the wafer contacts. To further enhance the electrical connection, the ECA material can be plasma etched to remove some of its polymer matrix and to expose the electrically conductive particles on one side and then plating with palladium.Type: GrantFiled: January 6, 2000Date of Patent: July 31, 2001Assignee: International Business Machines CorporationInventors: William E. Bernier, Michael A. Gaynes, Wayne J. Howell, Mark V. Pierson, Ajit K. Trivedi, Charles G. Woychik
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Patent number: 6256874Abstract: A method is provided for connecting two conductive layers in an electronic circuit package comprising the steps of forming dendrites on selected regions of a first conductive layer, forming dendrites on selected regions of a second conductive layer, applying an epoxy adhesive material over the first conductive layer, and compressively attaching the second conductive layer to the first conductive layer such that the dendrites on the first conductive layer contact the dendrites on the second conductive layer. Also claimed is an electronic circuit package incorporating the dendrites used for electrical interconnection manufactured in accordance with the present invention. An alternative embodiment of the invention utilizes an intermediate surface metal with dendrites in place of a “through via.Type: GrantFiled: May 20, 1999Date of Patent: July 10, 2001Assignee: International Business Machines CorporationInventors: Bernd K. Appelt, Saswati Datta, Michael A. Gaynes, John M. Lauffer, James R. Wilcox
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Publication number: 20010001183Abstract: A method for bonding heat sinks to packaged electronic components comprises the steps of: (a) exposing to a plasma a surface of a molded polymer formed on a substrate; (b) allowing the plasma to at least partially convert silicon-containing residue on the surface to silica; and (c) bonding an article to the surface by applying an adherent between the article and the surface. Often, the silicon-containing residue is silicone oil, a mold release compound, which may prevent the formation of a bond when using conventional bonding methods and materials. The silica layer formed on the surface of the molded polymer assists in formation of a proper bond. The plasma may be an oxygen plasma and the adherent may be selected from either a heat cured silicone-based paste adhesive with a metal oxide filler or a heat cured porous polymer film impregnated with adhesive.Type: ApplicationFiled: January 9, 2001Publication date: May 17, 2001Inventors: Frank D. Egitto, Michael A. Gaynes, Ramesh R. Kodnani, Luis J. Matienzo, Mark V. Pierson
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Patent number: 6219238Abstract: A structure for removably attaching a heat sink to an electronic package. At least one heat sink engaging member engages a surface of the heat sink opposite a surface of the heat sink engaging the electronic package. At least two heat sink retaining clips extend from opposite sides of the at least one heat sink engaging member. Each retaining clip includes a first arm for extending past a side of the heat sink and a portion of the electronic package and a second arm extending from the first member for engaging the electronic package.Type: GrantFiled: May 10, 1999Date of Patent: April 17, 2001Assignee: International Business Machines CorporationInventors: Frank E. Andros, Michael A. Gaynes, Hussain Shaukatullah, Wayne R. Storr
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Patent number: 6206997Abstract: A method for bonding heat sinks to packaged electronic components comprises the steps of: (a) exposing to a plasma a surface of a molded polymer formed on a substrate; (b) allowing the plasma to at least partially convert silicon-containing residue on the surface to silica; and (c) bonding an article to the surface by applying an adherent material between the article and the surface. Often, the silicon-containing residue is silicone oil, a mold release compound, which may prevent the formation of a bond when using conventional bonding methods and materials. The silica layer formed on the surface of the molded polymer assists in formation of a proper bond. The plasma may be an oxygen plasma and the adherent material may be selected from either a heat cured silicone-based paste adhesive with a metal oxide filler or a heat cured porous polymer film impregnated with adhesive.Type: GrantFiled: February 11, 1999Date of Patent: March 27, 2001Assignee: International Business Machines CorporationInventors: Frank D. Egitto, Michael A. Gaynes, Ramesh R. Kodnani, Luis J. Matienzo, Mark V. Pierson
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Patent number: 6199751Abstract: A technique of forming a metallurgical bond between pads on two surfaces is provided. A metal coating placed on each surface includes a first metal base layer and a second metal surface layer. The first and second metals include a low melting point constituent. A first ratio of the two metals forms a liquid phase with a second ratio of the two metals forming a solid phase. The volume of the base layer metal exceeds the volume necessary to form the solid phase between the base metal and the surface metal. Conductive metal particles are provided having a core metal and a coating metal dispersed in an uncured polymer material, at a volume fraction above the percolation threshold. The core metal and the coating metal together include a low melting point constituent. At a first ratio the components form a liquid phase and at a second ratio the two components form a solid phase.Type: GrantFiled: March 23, 2000Date of Patent: March 13, 2001Assignee: International Business Machines CorporationInventors: Michael A. Gaynes, Kostas I. Papathomas, Giana M. Phelan, Charles G. Woychik
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Patent number: 6193576Abstract: A method for aligning a plurality of thin film transistor tiles for constructing a flat panel display. A coverplate is arranged on a coverplate support. A first layer of a bonding material is applied to at least one of a first side of each of the tiles and a surface of the coverplate on which the tiles are to be secured. The tiles are arranged on the coverplate, such that the first layer of bonding material is arranged between the tiles and the coverplate. The tiles are connected to an alignment apparatus. The tiles are aligned relative to each other and the coverplate. The tiles are at least partially secured to the coverplate.Type: GrantFiled: May 19, 1998Date of Patent: February 27, 2001Assignee: International Business Machines CorporationInventors: Michael A. Gaynes, Allan O. Johnson, Ramesh R. Kodnani, Mark V. Pierson, Edward J. Tasillo
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Patent number: 6174406Abstract: Two surfaces are adhesively bonded together by providing on one of the surfaces a central, single point adhesive contact deposit and providing on one of the surfaces, adhesive extending from a central point deposit in a spoke-like array diagonally across substantially the entire surface. Also provided is the article obtained by the above method as well as the assembly used for bonding the two surfaces together. The surfaces are brought together, one on top of the other, with the adhesive located between the surfaces to cause the adhesive to spread out and cover the surfaces to thereby bond them together.Type: GrantFiled: April 9, 1998Date of Patent: January 16, 2001Assignee: International Business Machines CorporationInventors: Michael A. Gaynes, Ramesh R. Kodnani