Abstract: A substrate has a top side and a bottom side. A solar cell is secured to the top side of the substrate and has an anode and a cathode. A heat transfer element is secured to the bottom side of the substrate. An anode pad is formed on the top side of the substrate and is coupled to the anode of the solar cell; similarly, a cathode pad is formed on the top side of the substrate and is coupled to the cathode of the solar cell. The substrate coefficient of thermal expansion and the solar cell coefficient of thermal expansion match within plus or minus ten parts per million per degree C.

Abstract: A method of fabricating a chip package is provided. The chip package includes a laminate, a chip and conductive elements interposed between the chip and the laminate by which signals are transmitted among the chip and the laminate. The method includes dispensing a first underfill in a space defined between opposing faces of the chip and the laminate and dispensing a second underfill at least at a portion of an edge of the chip, the second underfill including a high aspect ratio material.

Abstract: Techniques provide improved thermal interface material application in an assembly associated with an integrated circuit package. For example, an apparatus comprises an integrated circuit module, a printed circuit board, and a heat transfer device. The integrated circuit module is mounted on a first surface of the printed circuit board. The printed circuit board has at least one thermal interface material application via formed therein in alignment with the integrated circuit module. The heat transfer device is mounted on a second surface of the printed circuit board and is thermally coupled to the integrated circuit module. The second surface of the printed circuit board is opposite to the first surface of the printed circuit board.

Abstract: A method of fabricating a chip package is provided. The chip package includes a laminate, a chip and conductive elements interposed between the chip and the laminate by which signals are transmitted among the chip and the laminate. The method includes dispensing a first underfill in a space defined between opposing faces of the chip and the laminate and dispensing a second underfill at least at a portion of an edge of the chip, the second underfill including a high aspect ratio material.

Abstract: An electric potential is applied to first and second electrodes on opposite sides of a gap between an electronic component and a heat spreader. At least one of a thermal interface material in the gap, the electronic component and the heat spreader is subjected to a changing physical condition. The electrical capacitance between the electrodes is monitored during the changing physical condition. Such a method can be practiced using an array of components sharing a common heat spreader. An assembly for testing thermal interfaces includes a printed circuit board, a plurality of electronic components mounted to and operatively associated with the printed circuit board, a heat spreader positioned for absorbing heat generated by the electronic components, a first electrode associated with the heat spreader, a plurality of second electrodes associated, respectively, with the electronic component, and a device for monitoring electrical capacitances between the first and second electrodes.

Abstract: Semiconductor package structures are provided which are designed to have liquid coolers integrally packaged with first level chip modules. In particular, apparatus for integrally packaging a liquid cooler device within a first level chip package structure include structures in which a liquid cooler device is thermally coupled directly to the back side of an integrated circuit chip flip-chip mounted on flexible chip carrier substrate. The liquid cooler device is mechanically coupled to the package substrate through a metallic stiffener structure that is bonded to the flexible package substrate to provide mechanical rigidity to the flexible package substrate.

Abstract: A method for detecting soft errors in an integrated circuit (IC) due to transient-particle emission, the IC comprising at least one chip and a substrate includes mixing an epoxy with a radioactive source to form a hot underfill (HUF); underfilling the chip with the HUF; sealing the underfilled chip; measuring a radioactivity of the HUF at an edge of the chip; measuring the radioactivity of the HUF on a test coupon; testing the IC for soft errors by determining a current radioactivity of the HUF at the time of testing based on the measured radioactivity; and after the expiration of a radioactive decay period of the radioactive source, using the IC in a computing device by a user.

Abstract: A low thermal conductivity material layer covers a peripheral portion of the bottom surface of the conductive plate of a chip bonder head. The center portion of the conductive plate is exposed or covered with another conductive plate laterally surrounded by the low thermal conductivity material layer. During bonding, the chip bonder head holds a first substrate upside down and heats the first substrate through the conductive plate. Heating of a fillet, i.e., the laterally extruding portion, of a pre-applied underfill material is reduced because the temperature at the exposed surfaces of the low thermal conductivity material layer is lower than the temperature at the bottom surface of the conductive plate. The longer curing time and the more uniform shape of the fillet in the bonded structure enhance the structural reliability of the bonded substrates.

Abstract: Semiconductor package structures are provided which are designed to have liquid coolers integrally packaged with first level chip modules. In particular, apparatus for integrally packaging a liquid cooler device within a first level chip package structure include structures in which a liquid cooler device is thermally coupled directly to the back side of an integrated circuit chip flip-chip mounted on flexible chip carrier substrate. The liquid cooler device is mechanically coupled to the package substrate through a metallic stiffener structure that is bonded to the flexible package substrate to provide mechanical rigidity to the flexible package substrate.

Abstract: An apparatus for reducing EMI at the micro-electronic-component level includes a substrate having a ground conductor integrated therein. A micro-electronic component such as an integrated circuit is mounted to the substrate. An electrically conductive lid is mounted to the substrate, thereby forming a physical interface with the substrate. The electrically conductive lid substantially covers the micro-electronic component. A conductive link is provided to create an electrical connection between the electrically conductive lid and the ground conductor at the physical interface.

Abstract: Disclosed are thermally conductive plates. Each plate is configured such that a uniform adhesive-filled gap may be achieved between the plate and a heat generating structure when the plate is bonded to the heat generating structure and subjected to a temperature within a predetermined temperature range that causes the heat generating structure to warp. Additionally, this disclosure presents the associated methods of forming the plates and of bonding the plates to a heat generating structure. In one embodiment the plate is curved and modeled to match the curved surface of a heat generating structure within the predetermined temperature range. In another embodiment the plate is a multi-layer conductive structure that is configured to undergo the same warpage under a thermal load as the heat generating structure. Thus, when the plate is bonded with the heat generating structure it is able to achieve and maintain a uniform adhesive-filled gap at any temperature.

Abstract: A process for measuring the thickness of an insulating material. The process includes providing a device used to measure capacitance, and electrically connecting the capacitance measuring device to a heat sink and an electrical, heat-generating component. The thickness of the insulating material is determined by measuring the capacitance of the insulating material according to tile formula: B=?r?oA/C, where B is the thickness of the insulating material, C is tile capacitance, A is the area of tile heat generating component, ?o is the permittivity of free space and ?r is the relative dielectric constant of the insulating material.

Abstract: To prevent formation of entrapped underfill material between solder balls and bonding bumps, fast temperature ramping is employed during a chi assembly after application of an underfill material prior to bonding. Voids formed within the underfill material are subsequently removed by curing the underfill material in a pressurized environment. Temperature cycling on the underfill material is limited during the bonding process in order to maintain viscosity of the underfill material prior to the cure process in the pressurized environment. Further, the underfill material is subjected to the pressurized environment until the cure process is complete to prevent re-formation of voids. The cure process can be a constant temperature or a multi-temperature process including temperature ramping. Further, the cure process can be a constant pressure process or a pressure cycling process that accelerates removal of the voids.

Abstract: A method of fabricating a chip package is provided. The chip package includes a laminate, a chip and conductive elements interposed between the chip and the laminate by which signals are transmitted among the chip and the laminate. The method includes dispensing a first underfill in a space defined between opposing faces of the chip and the laminate and dispensing a second underfill at least at a portion of an edge of the chip, the second underfill including a high aspect ratio material.

Abstract: A process for measuring the thickness of an insulating material. The process includes providing a device used to measure capacitance, and electrically connecting the capacitance measuring device to a heat sink and an electrical, heat-generating component. The thickness of the insulating material is determined by measuring the capacitance of the insulating material according to the formula; B=?r?oA/C, where B is the thickness of the insulating material, C is the capacitance, A is the area of the heat generating component, ?o is the permittivity of free space and ?r is the relative dielectric constant of the insulating material.

Abstract: Composite interconnect structure forming methods using injection molded solder are disclosed. The methods provide a mold having at least one opening formed therein with each opening including a member of a material dissimilar to a solder to be used to fill the opening, and then fill the remainder of each opening with solder to form the composite interconnect structure. The resulting composite interconnect structure can be leveraged to achieve a much larger variety of composite structures than exhibited by the prior art. For example, the material may be chosen to be more electrically conductive than the solder portion, more electromigration-resistant than the solder portion and/or more fatigue-resistant than the solder portion. In one embodiment, the composite interconnect structure can include an optical structure, or plastic or ceramic material.

Abstract: A process for measuring the thickness of an insulating material. The process includes providing a device used to measure capacitance, and electrically connecting the capacitance measuring device to a heat sink and an electrical, heat-generating component. The thickness of the insulating material is determined by measuring the capacitance of the insulating material according to the formula; B=?r?oA/C, where B is the thickness of the insulating material, C is the capacitance, A is the area of the heat generating component, ?o is the permittivity of free space and ?r is the relative dielectric constant of the insulating material.

Abstract: An electrically conductive adhesive (ECA) with low and stable contact resistance includes at least one melt-processable reactive resin, at least one reactive diluent, at least one rheological additive, copper particles, at least one curing agent and at least one organic acid catalyst. The ECA is useful for filling vias, and bonding together components of electronic circuit structures.

Abstract: The present invention is directed to soldering techniques and compositions for use therein. In one aspect, a flux composition is provided. The flux composition comprises a fluxing agent comprising organic acid, an organic tacking agent and an organic wetting agent. In another aspect, a soldering method for joining objects is provided comprising the following steps. A flux composition and a solder compound are applied to at least a portion of one or more of the objects. The flux composition comprises a fluxing agent comprising organic acid, an organic tacking agent and an organic wetting agent. The objects are then joined.

Abstract: Curved surfaces of a preform of thermoplastic adhesive provide improved regulation of heating and exclusion of gas as surfaces to be bonded are heated and pressed against the thermoplastic adhesive preform. Particulate or filamentary materials can be added to the thermoplastic adhesive for adjustment of coefficient of thermal expansion or further increase of heat transfer through the adhesive or both. The preform is preferably fabricated by molding, preferably in combination with die-cutting of a preform of desired volume from a web of approximately the same thickness as the completed bond.