Abstract: A method of forming metal lines that are aligned to underlying metal features that includes forming a neutral layer atop a hardmask layer that is overlying a dielectric layer. The neutral layer is composed of a neutral charged di-block polymer. Patterning the neutral layer, the hardmask layer and the dielectric layer to provide openings that are filled with a metal material to provide metal features. A self-assembled di-block copolymer material is deposited on a patterned surface of the neutral layer and the metal features. The self-assembled di-block copolymer material includes a first block composition with a first affinity for alignment to the metal features. The first block composition of the self-assembled di-block copolymer is converted to a metal that is self-aligned to the metal features.

Abstract: A semiconductor device including a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer may include a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of the suspended channel structures. The inner spacer may include a crescent shape with a substantially central seam.

Abstract: A method for manufacturing a field effect transistor includes chelating a molecular mask to a replacement metal gate in a field effect transistor. The method may further include forming a patterned dielectric layer on a bulk dielectric material and a gate dielectric barrier in one or more deposition steps. The method may include removing the molecular mask and exposing part of the gate dielectric barrier before depositing a dielectric cap that touches the gate dielectric barrier and the replacement metal gate.

Abstract: A semiconductor device including a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer may include a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of the suspended channel structures. The inner spacer may include a crescent shape with a substantially central seam.

Abstract: A semiconductor device including a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer may include a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of the suspended channel structures. The inner spacer may include a crescent shape with a substantially central seam.

Abstract: A semiconductor device including a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer may include a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of the suspended channel structures. The inner spacer may include a crescent shape with a substantially central seam.

Abstract: After forming a laterally contacting pair of a semiconductor fin and a conductive strap structure overlying a deep trench capacitor embedded in a substrate and forming a gate stack straddling a body region of the semiconductor fin, source/drain regions are formed in portions the semiconductor fin located on opposite sides of the gate stack by ion implantation. Next, a metal layer is applied over the source/drain region and subsequent annealing consumes entire source/drain regions to provide fully alloyed source/drain regions. A post alloyzation ion implantation is then performed to introduce dopants into the fully alloyed source/drain regions followed by an anneal to segregate the implanted dopants at interfaces between the fully alloyed source/drain regions and the body region of the semiconductor fin.

Abstract: In one aspect, a method of forming a CMOS device includes forming nanowires suspended over a BOX, wherein a first/second one or more of the nanowires are suspended at a first/second suspension height over the BOX, and wherein the first suspension height is greater than the second suspension height; depositing a conformal gate dielectric on the BOX and around the nanowires wherein the conformal gate dielectric deposited on the BOX is i) in a non-contact position with the conformal gate dielectric deposited around the first one or more of the nanowires, and ii) is in direct physical contact with the conformal gate dielectric deposited around the second one or more of the nanowires such that the BOX serves as an oxygen source during growth of a conformal oxide layer at the interface between the conformal gate dielectric and the second one or more of the nanowires.

Abstract: After forming a material stack including, from bottom to top, a dielectric material layer, a transfer layer, a hard mask layer and a neutral layer over a substrate, the neutral layer and the hard mask layer is patterned to create trenches therein that correspond to areas where unnecessary lines generated by a self-assembly of a self-assembling material subsequently formed and/or unnecessary portions of such lines are present. The self-assembling material is applied over the top surfaces of the patterned neutral layer and the transfer layer to form a self-aligned lamellar structure including alternating first and second domains. The second domains are removed selective to the first domains to provide a directed self-assembly (DSA) pattern of the first domains. Portions of the first domains not intersecting the trenches can be transferred into the patterned hard mask layer, resulting in a composite pattern of a pattern of trenches and the DSA pattern.

Abstract: After formation of a template layer over a neutral polymer layer, a self-assembling block copolymer material is applied and self-assembled. The template layer includes a first linear portion, a second linear portion that is shorter than the first linear portion, and blocking template structures having a greater width than the second linear portion. The self-assembling block copolymer material is phase-separated into alternating lamellae in regions away from the widthwise-extending portion. The blocking template structures perturb, and cause termination of, the lamellae. A cavity parallel to the first and second linear portions and terminating in self-alignment to the blocking template structures is formed upon selective removal of a polymeric block component. The pattern of the cavity can be inverted and transferred into the material layer to form fins having different lengths.

Abstract: A method for design template pattern optimization, comprises receiving a design for a fin field effect transistor (FinFET) device, wherein the design includes a configuration of fins, creating a design template pattern for the design for use in connection with directed self-assembly (DSA) patterning using graphoepitaxy, and optimizing the design template pattern to minimize pattern density gradients, wherein the design template pattern includes a plurality of guiding lines for guiding a block-copolymer deposited during the DSA patterning and the optimizing comprises altering the guiding lines.

Abstract: After forming spacers over a hard mask layer using a sidewall image transfer process, a neutral material layer is formed on the portions of the hard mask layer that are not covered by the spacers. The spacers and the neutral material layer guide the self-assembly of a block copolymer material. The microphase separation of the block copolymer material provides a lamella structure of alternating domains of the block copolymer material.

Abstract: A method for forming a semiconductor device comprising forming a stack of nanowires, the stack including a first nanowire having a first length, and a second nanowire having a second length, the second nanowire arranged above the first nanowire, forming a sacrificial gate stack on the stack of nanowires, growing a source/drain region on the first, second nanowires, removing the sacrificial gate stack to expose channel regions of the first and second nanowires, and forming a gate stack over the channel regions.

Abstract: In one aspect, a method of forming a CMOS device with multiple transistors having different Vt's is provided which includes: forming nanowires and pads on a wafer, wherein the nanowires are suspended at varying heights above an oxide layer of the wafer; and forming gate stacks of the transistors at least partially surrounding portions of each of the nanowires by: i) depositing a conformal gate dielectric around the nanowires and on the wafer beneath the nanowires; ii) depositing a conformal workfunction metal on the conformal gate dielectric around the nanowires and on the wafer beneath the nanowires, wherein an amount of the conformal workfunction metal deposited around the nanowires is varied based on the varying heights at which the nanowires are suspended over the oxide layer; and iii) depositing a conformal poly-silicon layer on the conformal workfunction metal around the nanowires and on the wafer beneath the nanowires.

Abstract: A method for design template pattern optimization, comprises receiving a design for a fin field effect transistor (FinFET) device, wherein the design includes a configuration of fins, creating a design template pattern for the design for use in connection with directed self-assembly (DSA) patterning using graphoepitaxy, and optimizing the design template pattern to minimize pattern density gradients, wherein the design template pattern includes a plurality of guiding lines for guiding a block-copolymer deposited during the DSA patterning and the optimizing comprises altering the guiding lines.

Abstract: Silicided nanowires as nanobridges in Josephson junctions. A superconducting silicided nanowire is used as a weak-link bridge in a Josephson junction, and a fabrication process is employed to produce silicided nanowires that includes patterning two junction banks and a rough nanowire from a silicon substrate, reshaping the nanowire through hydrogen annealing, and siliciding the nanowire by introduction of a metal into the nanowire structure.

Abstract: A semiconductor device includes a first source/drain region a second source/drain region, and a gate region interposed between the first and second source/drain regions. At least one nanowire has a first end anchored to the first source/drain region and an opposing second end anchored to the second source/drain region such that the nanowire is suspended above the wafer in the gate region. At least one gate electrode is in the gate region. The gate electrode contacts an entire surface of the nanowire to define a gate-all-around configuration. At least one pair of oxidized spacers surrounds the at least one gate electrode to electrically isolate the at least one gate electrode from the first and second source/drain regions.

Abstract: A semiconductor device includes a first source/drain region a second source/drain region, and a gate region interposed between the first and second source/drain regions. At least one nanowire has a first end anchored to the first source/drain region and an opposing second end anchored to the second source/drain region such that the nanowire is suspended above the wafer in the gate region. At least one gate electrode is in the gate region. The gate electrode contacts an entire surface of the nanowire to define a gate-all-around configuration. At least one pair of oxidized spacers surrounds the at least one gate electrode to electrically isolate the at least one gate electrode from the first and second source/drain regions.

Abstract: In one aspect, a method of forming a CMOS device includes forming nanowires suspended over a BOX, wherein a first/second one or more of the nanowires are suspended at a first/second suspension height over the BOX, and wherein the first suspension height is greater than the second suspension height; depositing a conformal gate dielectric on the BOX and around the nanowires wherein the conformal gate dielectric deposited on the BOX is i) in a non-contact position with the conformal gate dielectric deposited around the first one or more of the nanowires, and ii) is in direct physical contact with the conformal gate dielectric deposited around the second one or more of the nanowires such that the BOX serves as an oxygen source during growth of a conformal oxide layer at the interface between the conformal gate dielectric and the second one or more of the nanowires.

Abstract: A memory cell, an array of memory cells, and a method for fabricating a memory cell with multigate transistors such as fully depleted finFET or nano-wire transistors in embedded DRAM. The memory cell includes a trench capacitor, a non-planar transistor, and a self-aligned silicide interconnect electrically coupling the trench capacitor to the non-planar transistor.