Abstract: A method of making a field-effect transistor device includes providing a substrate with a fin stack having: a first sacrificial material layer on the substrate, a first semiconductive material layer on the first sacrificial material layer, and a second sacrificial material layer on the first semiconductive material layer. The method includes inserting a dummy gate having a second thickness, a dummy void, and an outer end that is coplanar to the second face. The method includes inserting a first spacer having a first thickness and a first void, and having an outer end that is coplanar to the first face. The method includes etching the first sacrificial material layer in the second plane and the second sacrificial material layer in the fourth plane. The method includes removing, at least partially, the first spacer. The method also includes inserting a second spacer having the first thickness.

Abstract: A method of making a field-effect transistor device includes providing a substrate with a fin stack having: a first sacrificial material layer on the substrate, a first semiconductive material layer on the first sacrificial material layer, and a second sacrificial material layer on the first semiconductive material layer. The method includes inserting a dummy gate having a second thickness, a dummy void, and an outer end that is coplanar to the second face. The method includes inserting a first spacer having a first thickness and a first void, and having an outer end that is coplanar to the first face. The method includes etching the first sacrificial material layer in the second plane and the second sacrificial material layer in the fourth plane. The method includes removing, at least partially, the first spacer. The method also includes inserting a second spacer having the first thickness.

Abstract: A semiconductor device and a method for manufacturing the device. The method includes: depositing a first dielectric layer on a semiconductor device; forming a plurality of first trenches through the first dielectric layer; depositing an insulating fill in the plurality of first trenches; planarizing the plurality of first trenches; forming a first gate contact between the plurality of first trenches; depositing a first contact fill in the first gate contact; planarizing the first gate contact; depositing a second dielectric layer on the device; forming a plurality of second trenches through the first and second dielectric layers; depositing a conductive fill in the plurality of second trenches; planarizing the plurality of second trenches; forming a second gate contact where the second gate contact is in contact with the first gate contact; depositing a second contact fill in the second gate contact; and planarizing the second gate contact.

Abstract: A semiconductor device including a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer may include a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of the suspended channel structures. The inner spacer may include a crescent shape with a substantially central seam.

Abstract: Various embodiments are directed toward a circuit configured to act as a Josephson junction. The circuit includes: a junction stack on a substrate, the junction stack including a portion of a first superconductor electrode, with an interface layer on a top side of the first superconductor electrode and configured to act as a tunneling barrier for the junction stack. The circuit may also comprise a first portion of a second superconductor electrode on top of the interface layer. A spacer may separate the portion of the first superconductor electrode in the junction stack from a second portion of the second superconductor electrode outside the junction stack where the second superconductor electrode overlays the first superconductor electrode.

Abstract: A memory device includes six field effect transistors (FETs) formed with semiconductor nanowires arranged on a substrate in an orientation substantially perpendicular to the substrate. The semiconductor nanowires have bottom contacts, gate contacts separated in a direction perpendicular to the substrate from the bottom contacts, and top contacts separated in a direction perpendicular to the substrate from the gate contacts. The necessary connections are made among the bottom, gate, and top contacts to form the memory device using first, second, and third metallization layers, the first metallization layer being separated in a direction perpendicular to the substrate from the top contacts, the second metallization layer being separated in a direction perpendicular to the substrate from the first metallization layer, and the third metallization layer being separated in a direction perpendicular to the substrate from the second metallization layer.

Abstract: A semiconductor device including a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer may include a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of the suspended channel structures. The inner spacer may include a crescent shape with a substantially central seam.

Abstract: After forming spacers over a hard mask layer using a sidewall image transfer process, a neutral material layer is formed on the portions of the hard mask layer that are not covered by the spacers. The spacers and the neutral material layer guide the self-assembly of a block copolymer material. The microphase separation of the block copolymer material provides a lamella structure of alternating domains of the block copolymer material.

Abstract: A semiconductor device that includes a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer includes a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of at least two suspended channel structures. The inner spacer may be composed of an n-type or p-type doped glass.

Abstract: A method for manufacturing a semiconductor device includes forming a stacked configuration of first and second semiconductor layers on a semiconductor substrate, wherein the stacked configuration comprises a repeating arrangement of a second semiconductor layer stacked on a first semiconductor layer, forming a plurality of dummy gates spaced apart from each other on the stacked configuration, wherein the plurality of dummy gates cover a portion of the stacked configuration in a channel region, performing an implantation of a semiconductor material on exposed portions of the stacked configuration in a source/drain region, wherein the implantation increases a concentration of the semiconductor material in the exposed portions of the stacked configuration, and selectively removing first semiconductor layers having an increased concentration of the semiconductor material from the source/drain region, wherein the removed first semiconductor layers correspond in position to the first semiconductor layers in the cha

Abstract: A method for manufacturing a semiconductor device includes forming a stacked configuration of first and second semiconductor layers on a semiconductor substrate, wherein the stacked configuration comprises a repeating arrangement of a second semiconductor layer stacked on a first semiconductor layer, forming a plurality of dummy gates spaced apart from each other on the stacked configuration, wherein the plurality of dummy gates cover a portion of the stacked configuration in a channel region, performing an implantation of a semiconductor material on exposed portions of the stacked configuration in a source/drain region, wherein the implantation increases a concentration of the semiconductor material in the exposed portions of the stacked configuration, and selectively removing first semiconductor layers having an increased concentration of the semiconductor material from the source/drain region, wherein the removed first semiconductor layers correspond in position to the first semiconductor layers in the cha

Abstract: Various embodiments are directed toward a circuit configured to act as a Josephson junction. The circuit includes: a junction stack on a substrate, the junction stack including a portion of a first superconductor electrode, with an interface layer on a top side of the first superconductor electrode and configured to act as a tunneling barrier for the junction stack. The circuit may also comprise a first portion of a second superconductor electrode on top of the interface layer. A spacer may separate the portion of the first superconductor electrode in the junction stack from a second portion of the second superconductor electrode outside the junction stack where the second superconductor electrode overlays the first superconductor electrode, the second portion of the second superconductor electrode contacting the substrate on at least one side of the spacer.

Abstract: The disclosure provides methods for directed self-assembly (DSA) of a block co-polymer (BCP). In one embodiment, a method includes: forming an oxide spacer along each of a first sidewall and a second sidewall of a cavity in a semiconductor substrate; forming a neutral layer between the oxide spacers and along a bottom of the cavity; and removing the oxide spacers to expose the first and second sidewalls and a portion of the bottom of the cavity adjacent the first and second sidewalls.

Abstract: A memory device includes six field effect transistors (FETs) formed with semiconductor nanowires arranged on a substrate in an orientation substantially perpendicular to the substrate. The semiconductor nanowires have bottom contacts, gate contacts separated in a direction perpendicular to the substrate from the bottom contacts, and top contacts separated in a direction perpendicular to the substrate from the gate contacts. The necessary connections are made among the bottom, gate, and top contacts to form the memory device using first, second, and third metallization layers, the first metallization layer being separated in a direction perpendicular to the substrate from the top contacts, the second metallization layer being separated in a direction perpendicular to the substrate from the first metallization layer, and the third metallization layer being separated in a direction perpendicular to the substrate from the second metallization layer.

Abstract: The disclosure provides methods for directed self-assembly (DSA) of a block co-polymer (BCP). In one embodiment, a method includes: forming an oxide spacer along each of a first sidewall and a second sidewall of a cavity in a semiconductor substrate; forming a neutral layer between the oxide spacers and along a bottom of the cavity; and removing the oxide spacers to expose the first and second sidewalls and a portion of the bottom of the cavity adjacent the first and second sidewalls.

Abstract: A method includes: growing a lattice of alternating sheets of tensile strained silicon and relaxed silicon-germanium on a substrate; isolating a first portion of the lattice from a second portion of the lattice; forming source regions and drain regions on each of the first portion of the lattice and the second portion of the lattice; forming a first gate opening in the first portion of the lattice and a second gate opening in the second portion of the lattice; selectively removing the sheets of relaxed silicon-germanium from under the second gate opening in the second portion of the lattice; selectively removing portions of the sheets of tensile strained silicon from under the first gate opening in the first portion of the lattice; and increasing a germanium content in the relaxed silicon-germanium layers under the first gate opening in the first portion of the lattice.

Abstract: A method of forming a wrap around contact, includes forming a plurality of semiconductor layers on a plurality of fin structures, forming a sacrificial gate on the plurality of semiconductor layers, forming an epitaxial layer on the plurality of fin structures and on a sidewall of the plurality of semiconductor layers, forming a gate structure by replacing the sacrificial gate and the plurality of semiconductor layers with a metal layer, and forming a wrap around contact on the epitaxial layer.

Abstract: A method of making a field-effect transistor device includes providing a substrate with a fin stack having: a first sacrificial material layer on the substrate, a first semiconductive material layer on the first sacrificial material layer, and a second sacrificial material layer on the first semiconductive material layer. The method includes inserting a dummy gate having a second thickness, a dummy void, and an outer end that is coplanar to the second face. The method includes inserting a first spacer having a first thickness and a first void, and having an outer end that is coplanar to the first face. The method includes etching the first sacrificial material layer in the second plane and the second sacrificial material layer in the fourth plane. The method includes removing, at least partially, the first spacer. The method also includes inserting a second spacer having the first thickness.

Abstract: A method, system, and non-transitory computer readable medium for reducing chemo-epitaxy directed-self assembly (DSA) defects of a guiding pattern layout, include inserting an internal dummy between a first portion of the guiding pattern and a second portion of the guiding pattern if a vertical spacing is equal to or greater than a first predetermined distance, inserting a first external dummy along an external edge of the guiding pattern in a vertical direction if the vertical spacing is greater than a second predetermined distance, and inserting an anti-taper structure on the first external dummy if a second distance from the external edge of the guiding pattern to the edge of the first external dummy is greater than a first distance.

Abstract: A semiconductor device includes a gate positioned on a substrate; a nanosheet that extends through the gate, protrudes from a sidewall of the gate, and forms a recess between the substrate and the nanosheet; a dielectric spacer disposed in the recess; a source/drain contact positioned on a source/drain disposed on the substrate adjacent to the gate; an air gap spacer positioned along the sidewall of the gate and in contact with a dielectric material disposed on the nanosheet, the air gap spacer being in contact with the source/drain contact; and an interlayer dielectric (ILD) disposed on the air gap spacer.