Abstract: A structure comprises a first channel region forming an n-channel device; a second channel region forming a p-channel device, the p-channel device being stacked with the n-channel device in a vertical orientation; a gate positioned around the stacked n-channel device and p-channel device; and at least one source region and at least one drain region extending from each of the n-channel device and the p-channel device. Each of the at least one source region and the at least one drain region within the stacked n-channel device and p-channel device are independently contacted.

Abstract: Field effect transistors and methods of forming the same include forming a stack of nanowires of alternating layers of channel material and sacrificial material. A layer of sacrificial material forms a top layer of the stack. A dummy gate is formed over the stack. Stack material outside of a region covered by the dummy gate is removed. The sacrificial material is etched to form recesses in the sacrificial material layers. Spacers are formed in the recesses in the sacrificial material layers. At least one pair of spacers is formed in recesses above an uppermost layer of channel material. The dummy gates are etched away. The top layer of sacrificial material protects an uppermost layer of channel material from damage from the anisotropic etch. The sacrificial material is etched away to expose the layers of channel material. A gate stack is formed over, around, and between the layers of channel material.

Abstract: Nanosheet semiconductor devices and methods of forming the same include forming a first stack having layers of a first material and layers of a second material. A second stack is formed having layers of a third material, layers of the second material, and a liner formed around the layers of the third material. A dummy gate stack is formed over channel regions of the first and second stacks. A passivating insulator layer is deposited around the dummy gate stacks. The dummy gate stacks are etched away. The second material is etched away after etching away the dummy gate stacks. Gate stacks are formed over and around the layers of first and second channel material to form respective first and second semiconductor devices.

Abstract: The disclosure provides methods for directed self-assembly (DSA) of a block co-polymer (BCP). In one embodiment, a method includes: forming an oxide spacer along each of a first sidewall and a second sidewall of a cavity in a semiconductor substrate; forming a neutral layer between the oxide spacers and along a bottom of the cavity; and removing the oxide spacers to expose the first and second sidewalls and a portion of the bottom of the cavity adjacent the first and second sidewalls.

Abstract: Embodiments of the invention are directed to methods of fabricating nanosheet channel field effect transistors. An example method includes forming a first sacrificial nanosheet and forming a first nanosheet stack over the first sacrificial nanosheet, wherein the first nanosheet stack includes alternating channel nanosheets and sacrificial nano sheets. The method further includes exposing a surface area of the first sacrificial nanosheet and exposing surface areas of the alternating channel nanosheets and sacrificial nanosheets, wherein the exposed surface area of the first sacrificial nanosheet is greater than each of the exposed surface areas of the alternating channel nanosheets and sacrificial nanosheets. The method further includes applying an etchant to the exposed surface areas, wherein the etchant is selective based at least in part on the amount of surface area to which the etchant is applied.

Abstract: A method is presented for forming a nanosheet metal oxide semiconductor field effect transistor (MOSFET) structure. The method includes forming a heteroepitaxial film stack including at least one sacrificial layer and at least one channel layer, patterning the heteroepitaxial film stack, forming a dummy gate stack with sidewall spacers, and forming a cladded or embedded epitaxial source/drain material along the patterned heteroepitaxial film stack sidewalls. The method further includes removing the dummy gate stack, partially removing the at least one sacrificial layer, and forming a replacement gate stack.

Abstract: A modified trench metal-semiconductor alloy formation method involves depositing a layer of a printable dielectric or a sacrificial carbon material within a trench structure and over contact regions of a semiconductor device, and then selectively removing the printable dielectric or sacrificial carbon material to segment the trench and form plural contact vias. A metallization layer is formed within the contact vias and over the contact regions.

Abstract: Hybrid pre-patterns were prepared for directed self-assembly of a given block copolymer capable of forming a lamellar domain pattern. The hybrid pre-patterns have top surfaces comprising independent elevated surfaces interspersed with adjacent recessed surfaces. The elevated surfaces are neutral wetting to the domains formed by self-assembly. Material below the elevated surfaces has greater etch-resistance than material below the recessed surfaces in a given etch process. Following other dimensional constraints of the hybrid pre-pattern described herein, a layer of the given block copolymer was formed on the hybrid pre-pattern. Self-assembly of the layer produced a lamellar domain pattern comprising self-aligned, unidirectional, perpendicularly oriented lamellae over the elevated surfaces, and parallel and/or perpendicularly oriented lamellae over recessed surfaces. The domain patterns displayed long range order along the major axis of the pre-pattern.

Abstract: In one aspect, a method of forming a local interconnect structure includes the steps of: forming a BOX SOI wafer having a fully depleted seed layer between a first BOX layer and a second BOX layer, and an active layer over the second BOX layer; forming at least one STI region in the active layer having an STI oxide; forming at least one trench that extends through the STI oxide and the second BOX layer down to the seed layer, wherein the trench has a footprint and a location such that a portion of the STI oxide remains lining sidewalls of the trench; and growing an epitaxial material in the trench using the seed layer as a template for the growth, wherein the epitaxial material is doped and serves as the local interconnect structure which is buried in the double BOX SOI wafer.

Abstract: A method of forming a nanosheet device, including forming a channel stack on a substrate, where the channel stack includes at least one nanosheet channel layer and at least one sacrificial release layer, forming a stack cover layer on at least a portion of the channel stack, forming a dummy gate on at least a portion of the stack cover layer, wherein at least a portion of the at least one nanosheet channel layer and at least one sacrificial release layer is exposed on opposite sides of the dummy gate, removing at least a portion of the at least one sacrificial release layer on each side of the dummy gate to form a sacrificial supporting rib, and forming an inner spacer layer on exposed portions of the at least one nanosheet channel layer and at least one sacrificial supporting rib.

Abstract: A method of forming a nanosheet device, including forming a channel stack on a substrate, where the channel stack includes at least one nanosheet channel layer and at least one sacrificial release layer, forming a stack cover layer on at least a portion of the channel stack, forming a dummy gate on at least a portion of the stack cover layer, wherein at least a portion of the at least one nanosheet channel layer and at least one sacrificial release layer is exposed on opposite sides of the dummy gate, removing at least a portion of the at least one sacrificial release layer on each side of the dummy gate to form a sacrificial supporting rib, and forming an inner spacer layer on exposed portions of the at least one nanosheet channel layer and at least one sacrificial supporting rib.

Abstract: A chemical pattern layer including an orientation control material and a prepattern material is formed over a substrate. The chemical pattern layer includes alignment-conferring features and additional masking features. A self-assembling material is applied and self-aligned over the chemical pattern layer. The polymeric block components align to the alignment-conferring features, while the alignment is not altered by the additional masking features. A first polymeric block component is removed selective to a second polymeric block component by an etch to form second polymeric block component portions having a pattern. A composite pattern of the pattern of an etch-resistant material within the chemical pattern layer and the pattern of the second polymeric block component portions can be transferred into underlying material layers employing at least another etch.

Abstract: A semiconductor device including a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer may include a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of the suspended channel structures. The inner spacer may include a crescent shape with a substantially central seam.

Abstract: Nanosheet semiconductor devices and methods of forming the same include forming a first nanosheet stack in a first device region with layers of a first channel material and layers of a sacrificial material. A second nanosheet stack is formed in a second device region with layers of a second channel material, layers of the sacrificial material, and a liner formed around the layers of the second channel material. The sacrificial material is etched away, but the liner protects the second channel material from the etch. Gate stacks are formed over and around the layers of first and second channel material to form respective first and second semiconductor devices in the first and second device regions.

Abstract: One example of an apparatus includes a conducting channel region. The conducting channel region includes a plurality of epitaxially grown, in situ doped conducting channels arranged in a spaced apart relation relative to each other. A source positioned at a first end of the conducting channel region, and a drain positioned at a second end of the conducting channel region. A gate surrounds all sides of the conducting channel region and fills in spaces between the plurality of epitaxially grown, in situ doped conducting channels.

Abstract: An electronic device is provided. The electronic device includes a semiconductor layer, a dielectric layer disposed on the semiconductor layer, circuitry disposed on the dielectric layer that includes interconnected cells, first contact line metallization and second contact line metallization, first power metallization disposed in-plane with or above the circuitry and second power metallization disposed in a trench defined in at least the dielectric layer. The electronic device further includes insulation disposed to insulate the second power metallization from the circuitry and the first power metallization at first locations and to permit electrical communication between the second power metallization, the circuitry and the first power metallization at second locations.

Abstract: A semiconductor device includes a plurality of gate stacks spaced apart from each other on a substrate, an etch stop layer formed on an upper surface of each gate stack, a dielectric cap layer formed on each etch stop layer, a plurality of source/drain regions formed on the substrate between respective pairs of adjacent gate stacks, and a plurality of contacts respectively corresponding to each source/drain region, wherein the contacts are separated from the gate structures and contact their corresponding source/drain regions.

Abstract: A method of forming a semiconductor structure includes depositing a first work function metal layer in nanosheet channel stacks for first and second CMOS structure each including a first nanosheet channel stack for an nFET and a second nanosheet channel stack for a pFET. The method also includes patterning to remove the first work function metal layer surrounding nanosheet channels in the first nanosheet channel stack of the first CMOS structure and nanosheet channels in the second nanosheet channel stack of the second CMOS structure. The method further includes depositing a second work function metal layer to surround the nanosheet channels in the first nanosheet channel stack of the first CMOS structure and the nanosheet channels in the second nanosheet channel stack of the second CMOS structure. The first CMOS structure has a first threshold voltage and the second CMOS structure has a second threshold voltage.

Abstract: Embodiments are directed to a method of forming a stacked nanosheet and resulting structures having equal thickness work function metal layers. A nanosheet stack is formed on a substrate. The nanosheet stack includes a first sacrificial layer formed on a first nanosheet. A hard mask is formed on the first sacrificial layer and the first sacrificial layer is removed to form a cavity between the hard mask and the first nanosheet. A work function layer is formed to fill the cavity between the hard mask and the first nanosheet.

Abstract: Semiconductor devices and methods of making the same include forming a stack of alternating layers of channel material and sacrificial material. The sacrificial material is etched away to free the layers of channel material. A gate stack is formed around the layers of channel material. At least one layer of channel material is deactivated. Source and drain regions are formed in contact with the at least one layer of active channel material.