Patents by Inventor Michael A Siegel

Michael A Siegel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6785137
    Abstract: A method for removing heat from an active area of an integrated circuit device is provided. The method includes applying a separator to the active area of the integrated circuit device. A thermally conductive element is coupled to the active area of the integrated circuit device outwardly of the separator.
    Type: Grant
    Filed: July 26, 2002
    Date of Patent: August 31, 2004
    Assignee: STMicroelectronics, Inc.
    Inventor: Harry Michael Siegel
  • Patent number: 6771500
    Abstract: The invention comprises a lid that is capable of being placed in contact with and attached to an integrated circuit that has an exposed surface of an integrated circuit die. The lid has portions that form a cavity between a surface of the lid and the exposed surface of the integrated circuit die when the lid is placed in contact with the integrated circuit. The lid also has portions that form a first fluid conduit for transporting a fluid into the cavity and a second fluid conduit for transporting the fluid out of the cavity. Heat from the integrated circuit die is absorbed by the fluid by direct convection and removed from the integrated circuit when the fluid is removed from the cavity.
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: August 3, 2004
    Assignee: STMicroelectronics, Inc.
    Inventors: Harry Michael Siegel, Anthony M. Chiu
  • Publication number: 20040017000
    Abstract: An integrated circuit (IC) device comprising: 1) an integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and sidewalls extending between the first surface and the second surface; 2) an integrated circuit (IC) package for supporting the IC die, wherein the IC package is attached to at least one of the sidewalls of the IC die such that at least a portion of the IC die first surface and at least a portion of the IC die second surface are exposed; and 3) at least one auxiliary component attached to at least one of the exposed portion of the IC die first surface and the exposed portion of the IC die second surface.
    Type: Application
    Filed: March 27, 2003
    Publication date: January 29, 2004
    Applicant: STMicroelectronics, Inc.
    Inventors: Anthony M. Chiu, Harry Michael Siegel
  • Publication number: 20040017661
    Abstract: A method for removing heat from an active area of an integrated circuit device is provided. The method includes applying a separator to the active area of the integrated circuit device. A thermally conductive element is coupled to the active area of the integrated circuit device outwardly of the separator.
    Type: Application
    Filed: July 26, 2002
    Publication date: January 29, 2004
    Applicant: STMicroelectronics, Inc.
    Inventor: Harry Michael Siegel
  • Publication number: 20030193072
    Abstract: A flat filter layer is received between upper and lower mold portions of a mold for packaging an integrated circuit sensor device, held by the mold over and in contact with the integrated circuit's sensing surface, in light compression between the sensing surface and a mold surface. The filter layer includes slots allowing passage of injected encapsulating material to cover the integrated circuit die, with overlap portions embedded in the encapsulating material, while preventing such encapsulating material from flowing onto the sensing surface. The filter layer may be, for example, a liquid and/or light filter, and may include a protective or supportive backing. The filter is thus affixed to the packaged integrated circuit sensor device, while mold residue is reduced and mold life extended.
    Type: Application
    Filed: April 16, 2002
    Publication date: October 16, 2003
    Applicant: STMICROELECTRONICS, INC.
    Inventors: Anthony M. Chiu, Harry Michael Siegel
  • Publication number: 20030167632
    Abstract: A system and method is disclosed for providing a redistribution metal layer in an integrated circuit. The redistribution metal layer is formed from the last metal layer in the integrated circuit during manufacture of the integrated circuit before final passivation is applied. The last metal layer provides sites for solder bump pads used in flip chip interconnection. The redistribution metal layer can be (1) a flat layer deposited over the next to last metal layer through an opening in a dielectric layer, or (2) deposited over an array of vias connected to the next to last metal layer. Space between the solder bump pads is deposited with narrower traces for connecting active circuit areas below. A final passivation layer is deposited to ensure product reliability.
    Type: Application
    Filed: March 6, 2002
    Publication date: September 11, 2003
    Applicant: STMicroelectronics, Inc.
    Inventors: Danielle A. Thomas, Harry Michael Siegel, Antonio A. Do Bento Vieira, Anthony M. Chiu
  • Patent number: 6614362
    Abstract: A method for an emergency vehicle alert system for transmitting signals from one or more emergency vehicles to a nearby commuter vehicle includes activating an initiation switch in one or more of the emergency vehicles. A transmitter located in each of the emergency vehicles, transmits a uniquely individual signal stamp of a predefined frequency and a GPS signal. Each emergency vehicle can be identified by the uniquely individual signal stamp. Other emergency vehicles and commuter vehicles in the area with the appropriate receiver can detect the transmitted signal stamp.
    Type: Grant
    Filed: June 18, 2001
    Date of Patent: September 2, 2003
    Inventor: Michael A Siegel
  • Patent number: 6603192
    Abstract: Passivation for capacitive sensor circuits, which overlies the capacitive sensor electrodes and is normally conformal to the electrodes and the underlying interlevel dielectric, is planarized by forming a layer of flowable oxide over the electrodes before forming the passivation. The flowable oxide, which is preferably very thin over the electrodes to minimize loss of sensitivity, provides a substantially planar upper surface, so that passivation formed on the flowable oxide is also substantially planar. Alternatively, a deposited oxide planarized by chemical mechanical polishing may be employed to planarize the surface on which a passivation stack is formed. The planarized passivation provides markedly improved scratch resistance.
    Type: Grant
    Filed: July 30, 1999
    Date of Patent: August 5, 2003
    Assignee: STMicroelectronics, Inc.
    Inventors: Danielle A. Thomas, Harry Michael Siegel
  • Publication number: 20030140678
    Abstract: A system and method is disclosed for aligning an integrated circuit die on an integrated circuit substrate. A plurality of deposits of deformable material are placed on the substrate where the integrated circuit die is to be aligned. In one advantageous embodiment a stamping tool is indexed to a first tooling hole and to a second tooling hole in the substrate. The stamping tool imprints the deposits of deformable material to a tolerance of less than one hundred microns with respect to the first and second tooling holes. The imprinted portions of the deposits to form a pocket for receiving the integrated circuit die. This enables the integrated circuit die to be precisely aligned on the substrate in three dimensions.
    Type: Application
    Filed: January 31, 2002
    Publication date: July 31, 2003
    Applicant: STMicroelectronics, Inc.
    Inventors: Harry Michael Siegel, Anthony M. Chiu
  • Publication number: 20030141595
    Abstract: A system and method is disclosed for providing mechanical planarization of a sequential build up substrate for an integrated circuit package. A planarization plate is placed in contact with an uneven external surface of a dielectric layer that covers underlying functional circuit elements and filler circuit elements. A heating element in the planarization plate flattens protruding portions of the external surface of the dielectric layer to create a flat external surface on the dielectric layer. After the flat external surface of the dielectric layer has cooled, it is then covered with a metal conductor layer. The method of the present invention increases the number of sequential buildup layers that may be placed on a sequential buildup substrate.
    Type: Application
    Filed: January 31, 2002
    Publication date: July 31, 2003
    Applicant: STMicroelectronics, Inc.
    Inventors: Anthony M. Chiu, Harry Michael Siegel
  • Publication number: 20030143406
    Abstract: A system and method is disclosed for using a pre-formed film in a transfer molding process of the type that uses a transfer mold to encapsulate portions of an integrated circuit with a molding compound. A film of compliant material is pre-formed to conform the shape of the film to a mold cavity surface of the transfer mold. The pre-formed film is then placed adjacent to the surfaces of the mold cavity of the transfer mold. The mold cavity is filled with molding compound and the integrated circuit is encapsulated. The pre-formation of the film allows materials to be used that are not suitable for use with prior art methods.
    Type: Application
    Filed: January 31, 2002
    Publication date: July 31, 2003
    Applicant: STMicroelectronics, Inc.
    Inventors: Harry Michael Siegel, Anthony M. Chiu
  • Patent number: 6600227
    Abstract: A system and method is disclosed for providing mechanical planarization of a sequential build up substrate for an integrated circuit package. A planarization plate is placed in contact with an uneven external surface of a dielectric layer that covers underlying functional circuit elements and filler circuit elements. A heating element in the planarization plate flattens protruding portions of the external surface of the dielectric layer to create a flat external surface on the dielectric layer. After the flat external surface of the dielectric layer has cooled, it is then covered with a metal conductor layer. The method of the present invention increases the number of sequential build up layers that may be placed on a sequential build up substrate.
    Type: Grant
    Filed: January 31, 2002
    Date of Patent: July 29, 2003
    Assignee: STMicroelectronics, Inc.
    Inventors: Anthony M. Chiu, Harry Michael Siegel
  • Publication number: 20030071287
    Abstract: Passivation for capacitive sensor circuits, which overlies the capacitive sensor electrodes and is normally conformal to the electrodes and the underlying interlevel dielectric, is planarized by forming a layer of flowable oxide over the electrodes before forming the passivation. The flowable oxide, which is preferably very thin over the electrodes to minimize loss of sensitivity, provides a substantially planar upper surface, so that passivation formed on the flowable oxide is also substantially planar. Alternatively, a deposited oxide planarized by chemical mechanical polishing may be employed to planarize the surface on which a passivation stack is formed. The planarized passivation provides markedly improved scratch resistance.
    Type: Application
    Filed: July 30, 1999
    Publication date: April 17, 2003
    Inventors: DANIELLE A. THOMAS, HARRY MICHAEL SIEGEL
  • Publication number: 20030043056
    Abstract: A method for an emergency vehicle alert system for transmitting signals from one or more emergency vehicles to a nearby commuter vehicle includes activating an initiation switch in one or more of the emergency vehicles. A transmitter located in each of the emergency vehicles, transmits a uniquely individual signal stamp of a predefined frequency and a GPS signal. Each emergency vehicle can be identified by the uniquely individual signal stamp. Other emergency vehicles and commuter vehicles in the area with the appropriate receiver can detect the transmitted signal stamp.
    Type: Application
    Filed: June 18, 2001
    Publication date: March 6, 2003
    Inventor: Michael A. Siegel
  • Patent number: 6411085
    Abstract: A depth and other characteristics of a ferromagnetic impurity in a workpiece of nonmagnetic material can be determined after demagnetizing of the workpiece by magnetizing the workpiece in a uniform field, preferably to saturation, and thereafter taking measurements of the field strength from the impurity at two different distances, forming a quotient or ratio of the measured values and determining the depth from a curve in which the signal ratio or quotient is plotted against the depth.
    Type: Grant
    Filed: April 18, 2000
    Date of Patent: June 25, 2002
    Assignees: Forschungszentrum Julich GmbH, Rolls-Royce Deutschland LTD & CO KG
    Inventors: Michael Siegel, Yuri Tavrin, Karl Schreiber, Armin Plath
  • Patent number: 6372543
    Abstract: An apparatus and method for producing a wrap-around interconnect substrate (60) comprising a substrate (42) having semi-circular vias (62) having openings (64) created by separating through cylindrical vias (62) that were positioned along cutting lines (46a, 46b) that formed part of an integrated circuit substrate strip (40) prior to separation, is disclosed.
    Type: Grant
    Filed: May 8, 2000
    Date of Patent: April 16, 2002
    Assignee: STMicroelectronics, Inc.
    Inventors: Anthony Chiu, Tom Quoc Lao, Harry Michael Siegel, Michael J. Hundt
  • Patent number: 6121678
    Abstract: An apparatus and method for producing a wrap-around interconnect substrate (60) comprising a substrate (42) having semi-circular vias (62) having openings (64) created by separating through cylindrical vias (62) that were positioned along cutting lines (46a, 46b) that formed part of an integrated circuit substrate strip (40) prior to separation, is disclosed.
    Type: Grant
    Filed: December 19, 1997
    Date of Patent: September 19, 2000
    Assignee: STMicroelectronics, Inc.
    Inventors: Anthony Chiu, Tom Quoc Lao, Harry Michael Siegel, Michael J. Hundt
  • Patent number: 5994774
    Abstract: A modular integrated circuit package is mounted on a surface of a printed circuit board. The integrated circuit package includes a rigid interposer releasably coupling a component module to a substrate member designed to be affixed to the printed circuit board. The substrate member has a first side with plural first electrical connectors for connection to the circuit board and a second side with second electrical connectors coupled to the first electrical connectors. The interposer includes a plurality of electrical connectors that couple electrical connectors of the component module to the second electrical connectors of the substrate member. The component module also includes plural clip members that engage a lower surface of the interposer to releasably couple the component module to the interposer.
    Type: Grant
    Filed: October 30, 1997
    Date of Patent: November 30, 1999
    Assignee: STMicroelectronics, Inc.
    Inventors: Harry Michael Siegel, Michael Joseph Hundt, Robert H. Bond