Abstract: An integrated circuit is provided with a protected circuit wherein a first FinFET operably coupled to a signal node is protected against electrostatic discharge voltage damage by a standard cell electrostatic discharge protection circuit which is connected between first and second voltage supplies and which includes a first FinFET diode connected between the signal node and the first voltage supply, and a second FinFET diode connected between the signal node and the second voltage supply, where the first and second FinFET diodes are each formed with a FinFET device comprising (1) a body well region forming a first diode terminal connected to one of the first or second voltage supplies, and (2) a shorted gate, source, and drain regions forming a second diode terminal connected to the signal node.

Abstract: A double IO pad cell including a busing frame formed on a busing metal layer aligned with a same-sized component frame integrated on a component layer of an IC. The busing frame includes first and second IO pads, a supply voltage rail, and a ground voltage rail. The component frame includes first and second primary ESD circuitry each including a first diode coupled between a respective one of the first and second IO pads and the supply voltage rail and a second diode coupled between the respective IO pad and the ground voltage rail. The second diodes of each primary ESD circuitry are integrated adjacent each other sandwiched between the first diodes which act as collector guard bands for the second diodes. The diodes of each primary ESD circuitry of the component frame are aligned with a corresponding one of the first and second IO pads of the busing frame.

Abstract: An integrated circuit is provided with a protected circuit wherein a first FinFET operably coupled to a signal node is protected against electrostatic discharge voltage damage by a standard cell electrostatic discharge protection circuit which is connected between first and second voltage supplies and which includes a first FinFET diode connected between the signal node and the first voltage supply, and a second FinFET diode connected between the signal node and the second voltage supply, where the first and second FinFET diodes are each formed with a FinFET device comprising (1) a body well region forming a first diode terminal connected to one of the first or second voltage supplies, and (2) a shorted gate, source, and drain regions forming a second diode terminal connected to the signal node.

Abstract: An electrostatic discharge (ESD) protection scheme is provided that reduces EMI noise propagation among functional circuit blocks of an integrated circuit (IC). Traditional ESD protection schemes include an ESD bus electrically tied to the substrate of an integrated circuit (e.g., a P-well) and substrate well regions associated with electromagnetic interference (EMI) aggressor and sensitive circuits. These electrical couplings can propagate EMI noise on the ESD bus throughout the circuit blocks of the IC. Embodiments provide an ESD bus that is not tied to the substrate well regions associated with EMI aggressor and sensitive circuits of the IC, but instead is a separate conductive layer electrically coupled to an external ground. In this manner, the device circuits are isolated from EMI noise carried in the ESD bus, thereby protecting the various functional blocks from such noise.

Abstract: An integrated circuit is formed on a substrate, and the integrated circuit includes first and second conductors for providing supply and ground voltages, respectively, a clamp device, and a trigger circuit. The clamp device includes first and second metal oxide semiconductor (MOS) transistors coupled in series between the first and second conductors, wherein the first and second MOS transistors include first and second gates, respectively. The trigger circuit is coupled between the first and second conductors and is configured to drive the first and second gates with first and second voltages, respectively, in response to an electrostatic discharge (ESD) event. The trigger circuit includes a biasing circuit for generating the first voltage as a function of the supply voltage, a PMOS transistor coupled between the first conductor and the second gate, wherein the PMOS transistors includes a third gate.

Abstract: An electrostatic discharge (ESD) protection scheme is provided that reduces EMI noise propagation among functional circuit blocks of an integrated circuit (IC). Traditional ESD protection schemes include an ESD bus electrically tied to the substrate of an integrated circuit (e.g., a P-well) and substrate well regions associated with electromagnetic interference (EMI) aggressor and sensitive circuits. These electrical couplings can propagate EMI noise on the ESD bus throughout the circuit blocks of the IC. Embodiments provide an ESD bus that is not tied to the substrate well regions associated with EMI aggressor and sensitive circuits of the IC, but instead is a separate conductive layer electrically coupled to an external ground. In this manner, the device circuits are isolated from EMI noise carried in the ESD bus, thereby protecting the various functional blocks from such noise.

Abstract: An apparatus for electrostatic discharge protection. In one embodiment, an integrated circuit (IC) includes a trigger circuit configured to generate a trigger voltage VT in response to an electrostatic discharge (ESD) event. A plurality of metal oxide semiconductor (MOS) transistors are coupled to the trigger circuit. The plurality of MOS transistors are configured to conduct ESD current from a plurality of circuit nodes, respectively, to a ground conductor in response to the trigger circuit generating the trigger voltage VT. A voltage limiter circuit is also included and is configured to limit the trigger voltage VT.

Abstract: An integrated circuit includes a power switch coupled between a first voltage supply node and an internal voltage supply node and a switch control circuit coupled to a control electrode of the power switch. The switch control circuit includes a driver circuit coupled between a second voltage supply node and a third voltage supply node, a pass-gate having a first node coupled to an output of the driver circuit and a second node coupled to the control electrode of the power switch, a pull-up transistor having a first current electrode coupled to the first voltage supply node, a second current electrode coupled to the control electrode of the power switch, and a bias circuit having a bias output configured to provide a higher voltage between the first and second power supply nodes as a bias voltage to a body electrode of the pull-up transistor.

Abstract: An electronic switch that includes a signal path with a first terminal side of the signal path including cascoded transistors in the signal path. When the switch is in an off state, the gate of one of the cascoded transistors is biased at an intermediate voltage different from the voltage applied to the gate of the other of the cascoded transistors. In one embodiment, having the gate of one of the cascoded transistors biased at an intermediate voltage in an off state may reduce leakage current into a signal terminal of the switch. The electronic switch includes an injection shunting device (e.g. such as a transistor) connected to a node of the signal path. In one embodiment, the injection shunting device prevents the voltage of the node from reaching a specific voltage level due to leakage current when the switch is in an off state.

Abstract: An electronic switch that includes a signal path with a first terminal side of the signal path including cascoded transistors in the signal path. When the switch is in an off state, the gate of one of the cascoded transistors is biased at an intermediate voltage different from the voltage applied to the gate of the other of the cascoded transistors. In one embodiment, having the gate of one of the cascoded transistors biased at an intermediate voltage in an off state may reduce leakage current into a signal terminal of the switch. The electronic switch includes an injection shunting device (e.g. such as a transistor) connected to a node of the signal path. In one embodiment, the injection shunting device prevents the voltage of the node from reaching a specific voltage level due to leakage current when the switch is in an off state.

Abstract: An apparatus for electrostatic discharge protection. In one embodiment, an integrated circuit (IC) includes a trigger circuit configured to generate a trigger voltage VT in response to an electrostatic discharge (ESD) event. A plurality of metal oxide semiconductor (MOS) transistors are coupled to the trigger circuit. The plurality of MOS transistors are configured to conduct ESD current from a plurality of circuit nodes, respectively, to a ground conductor in response to the trigger circuit generating the trigger voltage VT. A voltage limiter circuit is also included and is configured to limit the trigger voltage VT.

Abstract: A circuit includes a high voltage (HV) transistor having a first current electrode, a second current electrode, and a control electrode coupled to receive a control signal. The HV transistor is configured and arranged to be non-conductive when the control signal is at a first state and conductive when the control signal is at a second state. A low voltage (LV) transistor is coupled to the first current electrode of the HV transistor. An HV pad is coupled to the second current electrode of the HV transistor. An operating voltage rating of the HV pad exceeds an operating voltage rating of the LV transistor. A secondary electrostatic discharge protection device is coupled between the second current electrode of the HV transistor and a voltage supply terminal.

Abstract: An integrated circuit is formed on a substrate, and the integrated circuit includes first and second conductors for providing supply and ground voltages, respectively, a clamp device, and a trigger circuit. The clamp device includes first and second metal oxide semiconductor (MOS) transistors coupled in series between the first and second conductors, wherein the first and second MOS transistors include first and second gates, respectively. The trigger circuit is coupled between the first and second conductors and is configured to drive the first and second gates with first and second voltages, respectively, in response to an electrostatic discharge (ESD) event. The trigger circuit includes a biasing circuit for generating the first voltage as a function of the supply voltage, a PMOS transistor coupled between the first conductor and the second gate, wherein the PMOS transistors includes a third gate.

Abstract: An integrated circuit includes a power switch coupled between a first voltage supply node and an internal voltage supply node and a switch control circuit coupled to a control electrode of the power switch. The switch control circuit includes a driver circuit coupled between a second voltage supply node and a third voltage supply node, a pass-gate having a first node coupled to an output of the driver circuit and a second node coupled to the control electrode of the power switch, a pull-up transistor having a first current electrode coupled to the first voltage supply node, a second current electrode coupled to the control electrode of the power switch, and a bias circuit having a bias output configured to provide a higher voltage between the first and second power supply nodes as a bias voltage to a body electrode of the pull-up transistor.

Abstract: An integrated circuit with protection against transient electrical stress events includes a trigger circuit having a first detection circuit coupled to a first supply voltage, a second detection circuit coupled to a second supply voltage, and a rail clamp device. During a first type of electrical stress event, the rail clamp device is activated in response to a first output signal provided by the first detection circuit. During a second type of electrical stress event, the rail clamp device is activated in response to a second output signal provided by the second detection circuit.

Abstract: An integrated circuit for protecting against transient electrical stress events includes a rail clamp device, and a trigger circuit including a resistive-capacitive (RC) filter, a drive circuit including a first inverter stage receiving an input signal from the RC filter, the drive circuit is configured to enable the rail clamp device during a transient electrical stress event, and a stress event detection circuit coupled to the RC filter. The drive circuit includes a configurable activation voltage which is controlled by the stress event detection circuit, wherein the activation voltage is reduced when the transient electrical stress event is detected.

Abstract: An integrated circuit includes an I/O pad and a protection device coupled to the I/O pad and a first supply node. A transient event detector includes a latch; a first transistor having a first current electrode coupled to the I/O pad, a control electrode coupled to a first supply node, and a second current electrode coupled to a data input of the latch, wherein the latch is configured to store an indication that a transient event occurred. An event level sensor includes a first transistor having a first current electrode coupled to the I/O pad, a control electrode coupled to the protection device, and a second current electrode coupled to a load circuit; a rectifier device coupled between the second current electrode and a capacitor; a second transistor having a control electrode coupled to the capacitor; and an output circuit configured to place a current on a first sense bus proportional to a current through the load circuit.

Abstract: An integrated circuit with protection against transient electrical stress events includes a trigger circuit having a first detection circuit coupled to a first supply voltage, a second detection circuit coupled to a second supply voltage, and a rail clamp device. During a first type of electrical stress event, the rail clamp device is activated in response to a first output signal provided by the first detection circuit. During a second type of electrical stress event, the rail clamp device is activated in response to a second output signal provided by the second detection circuit.

Abstract: An integrated circuit with protection against transient electrical stress events includes a trigger circuit having a first detection circuit coupled to a first supply voltage, a second detection circuit coupled to a second supply voltage, and a rail clamp device. During a first type of electrical stress event, the rail clamp device is activated in response to a first output signal provided by the first detection circuit. During a second type of electrical stress event, the rail clamp device is activated in response to a second output signal provided by the second detection circuit.

Abstract: A transmission gate circuit includes a pass gate and a control circuit and provides High Voltage protection to a flash memory in a characterization mode and a low resistive path with true open-drain functionality in a normal mode. A native NMOSFET in series with the pass gate provides overvoltage protection for additional circuitry. Well biasing, gate tracking and internal node clamping circuits ensure that all of the devices of the pass gate and control circuit operated within safe operational voltage levels. The two modes of operation can be selected by an enable signal. The transmission gate circuit can support up to a 5.5 volts input in a true open drain mode while an input/output supply voltage of 3.3 volts is supplied.