Patents by Inventor Michael A. Stockinger
Michael A. Stockinger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8730625Abstract: An electrostatic discharge (ESD) protection circuit includes a clamping transistor and a trigger circuit. The clamping transistor is coupled between a first power supply voltage terminal and a second power supply voltage terminal. The trigger circuit includes a detection circuit, first and second transistors, and first, second, and third inverters. The detection circuit is coupled to monitor a power supply voltage. The first inverter has an input terminal coupled to a current electrode of the first transistor, and an output terminal coupled to a control electrode of the clamping transistor. The second inverter and the third inverter form a feedback path from the output of the first inverter to the control electrode of the first transistor. The second inverter has a switching voltage that is lower than a midpoint voltage of a power supply voltage provided to the first and second power supply voltage terminals.Type: GrantFiled: September 22, 2011Date of Patent: May 20, 2014Assignee: Freescale Semiconductor, Inc.Inventor: Michael A. Stockinger
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Patent number: 8456784Abstract: An overvoltage protection circuit may include a reference voltage generator, a trigger circuit, and a clamping device. The reference voltage generator is for providing a reference voltage that is relatively constant during a powered EOS/ESD event. The trigger circuit is coupled to receive the reference voltage and a power supply voltage. The trigger circuit is for comparing the reference voltage to the power supply voltage. In response to detecting that the power supply voltage is above the reference voltage, the trigger circuit provides a trigger signal having a voltage proportional to a voltage level of the overvoltage event. The clamping device is coupled between a first power supply terminal and a second power supply terminal. The clamping device is for providing a current path between the first and second power supply terminals in response to the trigger signal.Type: GrantFiled: May 3, 2010Date of Patent: June 4, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Michael A. Stockinger, Chris C. Dao, Dale J. McQuirk
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Publication number: 20130077195Abstract: An electrostatic discharge (ESD) protection circuit includes a clamping transistor and a trigger circuit. The clamping transistor is coupled between a first power supply voltage terminal and a second power supply voltage terminal. The trigger circuit includes a detection circuit, first and second transistors, and first, second, and third inverters. The detection circuit is coupled to monitor a power supply voltage. The first inverter has an input terminal coupled to a current electrode of the first transistor, and an output terminal coupled to a control electrode of the clamping transistor. The second inverter and the third inverter form a feedback path from the output of the first inverter to the control electrode of the first transistor. The second inverter has a switching voltage that is lower than a midpoint voltage of a power supply voltage provided to the first and second power supply voltage terminals.Type: ApplicationFiled: September 22, 2011Publication date: March 28, 2013Inventor: MICHAEL A. STOCKINGER
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Patent number: 8373953Abstract: Embodiments of the present disclosure provide an integrated circuit (IC) or semiconductor device. This semiconductor device includes a number of I/O pads or bumps on an outer surface of the semiconductor device, a number of electrostatic discharge (ESD) protection cells and functional modules. Individual ESD protection cells couple to and are downstream of individual I/O pads. Functional modules coupled to and are downstream of individual ESD protection cells. The ESD protection cells protect circuitry within the functional module from electrostatic discharge events. A rail clamp may provide an ESD discharge path between a first power supply bus and a second power supply bus. The ESD protection cells may be collected in groups to form clusters (with linear or irregular placement patterns). These clusters may be distributed autarchically across the semiconductor device overlapping one or more functional modules or within spaces or gaps between the functional modules.Type: GrantFiled: December 29, 2008Date of Patent: February 12, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Michael A Stockinger, Anthony G Dunne, Alex P Gerdemann, James W Miller, Daniel J O'Hare, Paul J Sheridan, Jeannie Han Millaway
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Publication number: 20130026576Abstract: An integrated circuit ESD protection circuit (270) is formed with a combination device consisting of a gated diode (271) and an output buffer MOSFET (272) where the body tie fingers of a first conductivity type (307) are formed in the substrate (301, 302) and isolated from the drain regions of a second conductivity type (310) using a plurality of diode poly fingers (231, 232) which are interleaved with a plurality of poly gate fingers (204, 205) forming the output buffer MOSFET (272).Type: ApplicationFiled: July 29, 2011Publication date: January 31, 2013Inventor: Michael A. Stockinger
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Patent number: 8274146Abstract: An integrated circuit includes a high speed circuit, an interconnect pad, a passivation layer under the interconnect pad, a first patterned metal layer, and a first via. The high speed circuit is for a high speed signal at a terminal of the high speed circuit. The interconnect pad is on a top surface of the integrated circuit structure. The first patterned metal layer is under the passivation layer having a first portion and a second portion. The first portion of the first patterned metal layer is connected to the terminal of the high speed circuit. The second portion of the first patterned metal layer is under the interconnect pad and is electrically floating when the high frequency signal is present on the interconnect pad portion. The result is reduced capacitive loading on the high speed signal which improves performance.Type: GrantFiled: May 30, 2008Date of Patent: September 25, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Michael A. Stockinger, Kevin J. Hess, James W. Miller
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Patent number: 8228109Abstract: A transmission gate circuit includes a first transmission gate, having a first switching device, coupled in series with a second transmission gate, having a second switching device, and control circuitry which places the first transmission gate and the second transmission gate into a conductive state to provide a conductive path through the first transmission gate and the second transmission gate. When the voltage of the first terminal is above a first voltage level and outside a safe operating voltage area of at least one of the first and second switching device, the first switching device remains within its safe operating voltage area and the second switching device remains within its safe operating voltage area.Type: GrantFiled: June 28, 2010Date of Patent: July 24, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Michael A. Stockinger, Jose A. Camarena, Wenzhong Zhang
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Publication number: 20110316610Abstract: A transmission gate circuit includes a first transmission gate, having a first switching device, coupled in series with a second transmission gate, having a second switching device, and control circuitry which places the first transmission gate and the second transmission gate into a conductive state to provide a conductive path through the first transmission gate and the second transmission gate. When the voltage of the first terminal is above a first voltage level and outside a safe operating voltage area of at least one of the first and second switching device, the first switching device remains within its safe operating voltage area and the second switching device remains within its safe operating voltage area.Type: ApplicationFiled: June 28, 2010Publication date: December 29, 2011Inventors: Michael A. Stockinger, Jose A. Camarena, Wenzhong Zhang
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Publication number: 20110267723Abstract: An overvoltage protection circuit may include a reference voltage generator, a trigger circuit, and a clamping device. The reference voltage generator is for providing a reference voltage that is relatively constant during a powered EOS/ESD event. The trigger circuit is coupled to receive the reference voltage and a power supply voltage. The trigger circuit is for comparing the reference voltage to the power supply voltage. In response to detecting that the power supply voltage is above the reference voltage, the trigger circuit provides a trigger signal having a voltage proportional to a voltage level of the overvoltage event. The clamping device is coupled between a first power supply terminal and a second power supply terminal. The clamping device is for providing a current path between the first and second power supply terminals in response to the trigger signal.Type: ApplicationFiled: May 3, 2010Publication date: November 3, 2011Inventors: Michael A. Stockinger, Chris C. Dao, Dale J. McQuirk
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Patent number: 7893696Abstract: A circuit is provided wherein a test pulse is provided to a device under test. A module allows the test pulse to pass through to the device under test. The module blocks a reflected pulse from passing through to the device under test when the reflected pulse has an opposite polarity from the polarity of the test pulse. In some cases, the reflected pulse may be detrimental to the device under test if it is not prevented from reaching the device under test. In one embodiment, when a second reflected test pulse is traveling away from the device under test, the module allows the second reflected test pulse to pass through.Type: GrantFiled: February 29, 2008Date of Patent: February 22, 2011Assignee: Freescale Semiconductor, Inc.Inventor: Michael A. Stockinger
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Patent number: 7777998Abstract: Circuitry on integrated circuits usually includes protection against electrostatic discharge (ESD) events. A second ESD current path may be provided in addition to a first ESD current path for shunting ESD current away from circuitry to be protected during an ESD event. In addition to the standard power and ground buses used to provide power and ground voltages to the protected circuitry, one or more extra power and/or ground buses and associated circuitry may be added for improved ESD protection.Type: GrantFiled: September 10, 2007Date of Patent: August 17, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Michael A. Stockinger, Michael G. Khazhinsky, James W. Miller
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Publication number: 20100165522Abstract: Embodiments of the present disclosure provide an integrated circuit (IC) or semiconductor device. This semiconductor device includes a number of I/O pads or bumps on an outer surface of the semiconductor device, a number of electrostatic discharge (ESD) protection cells and functional modules. Individual ESD protection cells couple to and are downstream of individual I/O pads. Functional modules coupled to and are downstream of individual ESD protection cells. The ESD protection cells protect circuitry within the functional module from electrostatic discharge events. A rail clamp may provide an ESD discharge path between a first power supply bus and a second power supply bus. The ESD protection cells may be collected in groups to form clusters (with linear or irregular placement patterns). These clusters may be distributed autarchically across the semiconductor device overlapping one or more functional modules or within spaces or gaps between the functional modules.Type: ApplicationFiled: December 29, 2008Publication date: July 1, 2010Inventors: Michael A. Stockinger, Anthony G. Dunne, Alex P. Gerdemann, James W. Miller, Daniel J. O'Hare, Paul J. Sheridan, Jeannie Han Millaway
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Publication number: 20090294970Abstract: An integrated circuit includes a high speed circuit, an interconnect pad, a passivation layer under the interconnect pad, a first patterned metal layer, and a first via. The high speed circuit is for a high speed signal at a terminal of the high speed circuit. The interconnect pad is on a top surface of the integrated circuit structure. The first patterned metal layer is under the passivation layer having a first portion and a second portion. The first portion of the first patterned metal layer is connected to the terminal of the high speed circuit. The second portion of the first patterned metal layer is under the interconnect pad and is electrically floating when the high frequency signal is present on the interconnect pad portion. The result is reduced capacitive loading on the high speed signal which improves performance.Type: ApplicationFiled: May 30, 2008Publication date: December 3, 2009Inventors: Michael A. Stockinger, Kevin J. Hess, James W. Miller
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Patent number: 7589945Abstract: An integrated circuit includes a first I/O cell disposed at a substrate, the first I/O cell including a first electrostatic discharge (ESD) clamp transistor device. The first ESD clamp transistor device includes a control electrode, a first current electrode coupled to a first voltage reference bus, and second current electrode coupled to a second voltage reference bus. The first ESD clamp transistor device has a first channel width. The integrated circuit further includes a second I/O cell including a second ESD clamp transistor device. The second ESD clamp transistor device includes a control electrode, a first current electrode coupled to the first voltage reference bus, and second current electrode coupled to the second voltage reference bus. The second ESD clamp transistor device has a second channel width different than the first channel width.Type: GrantFiled: August 31, 2006Date of Patent: September 15, 2009Assignee: Freescale Semiconductor, Inc.Inventors: James W. Miller, Melanie Etherton, Michael G. Khazhinsky, Michael Stockinger
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Publication number: 20090219038Abstract: A circuit is provided wherein a test pulse is provided to a device under test. A module allows the test pulse to pass through to the device under test. The module blocks a reflected pulse from passing through to the device under test when the reflected pulse has an opposite polarity from the polarity of the test pulse. In some cases, the reflected pulse may be detrimental to the device under test if it is not prevented from reaching the device under test. In one embodiment, when a second reflected test pulse is traveling away from the device under test, the module allows the second reflected test pulse to pass through.Type: ApplicationFiled: February 29, 2008Publication date: September 3, 2009Inventor: Michael A. Stockinger
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Publication number: 20090067104Abstract: Circuitry on integrated circuits usually includes protection against electrostatic discharge (ESD) events. A second ESD current path may be provided in addition to a first ESD current path for shunting ESD current away from circuitry to be protected during an ESD event. In addition to the standard power and ground buses used to provide power and ground voltages to the protected circuitry, one or more extra power and/or ground buses and associated circuitry may be added for improved ESD protection.Type: ApplicationFiled: September 10, 2007Publication date: March 12, 2009Inventors: Michael A. Stockinger, Michael G. Khazhinsky, James W. Miller
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Patent number: 7446990Abstract: An ESD protection system for I/O cells of an integrated circuit. The I/O cells of a bank of cells include a first type of I/O cells having ESD trigger circuits and a second type of I/O cells having ESD clamp devices. In one embodiment, the ESD trigger circuits of the first type are located at the same area of an active circuitry floor plan as the area in the floor plan for the ESD clamp devices of the I/O cells of the second type.Type: GrantFiled: February 11, 2005Date of Patent: November 4, 2008Assignee: Freescale Semiconductor, Inc.Inventors: James W. Miller, Michael G. Khazhinsky, Michael Stockinger, James C. Weldon
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Publication number: 20080062596Abstract: An integrated circuit includes a first I/O cell disposed at a substrate, the first I/O cell including a first electrostatic discharge (ESD) clamp transistor device. The first ESD clamp transistor device includes a control electrode, a first current electrode coupled to a first voltage reference bus, and second current electrode coupled to a second voltage reference bus. The first ESD clamp transistor device has a first channel width. The integrated circuit further includes a second I/O cell including a second ESD clamp transistor device. The second ESD clamp transistor device includes a control electrode, a first current electrode coupled to the first voltage reference bus, and second current electrode coupled to the second voltage reference bus. The second ESD clamp transistor device has a second channel width different than the first channel width.Type: ApplicationFiled: August 31, 2006Publication date: March 13, 2008Applicant: Freescale Semiconductor, Inc.Inventors: James W. Miller, Melanie Etherton, Michael G. Khazhinsky, Michael Stockinger
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Patent number: 7236339Abstract: An ESD protection circuit (81) and a method for providing ESD protection is provided. In some embodiments, an N-channel transistor (24), which can be ESD damaged, is selectively turned on and made conducting. The purpose of turning on the N-channel transistor (24) is to maximize the Vt1 of the N-channel transistor (24). Vt1 is the drain-to-source voltage point at which the parasitic bipolar action of the N-channel transistor (24) first occurs. In some embodiments, the ESD protection circuit (81) includes a diode (64) which provides an additional current path from the I/O pad 31 to a first power supply node (76).Type: GrantFiled: April 21, 2005Date of Patent: June 26, 2007Assignee: Freescale Semiconductor, Inc.Inventors: James W. Miller, Michael G. Khazhinsky, Michael Stockinger
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Patent number: 7209332Abstract: A transient detection circuit which may be used in an electrostatic discharge (ESD) clamp circuit. The transient detection circuit includes a filter circuit and an inverter circuit. The voltage switch point of the inverter circuit has a constant voltage offset from one of the nodes. When a filtered voltage level from the filter circuit crosses the voltage switch point of the inverter circuit (indicative of an ESD event), the inverter circuit provides a signal indicating an ESD event.Type: GrantFiled: December 10, 2002Date of Patent: April 24, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Michael Stockinger, James W. Miller