Abstract: In a layered composite including a substrate comprising a number of individual layers disposed on the substrate, at least one of the individual layers includes cubic boron nitride formed by material deposition, the cubic boron nitride including oxygen added during deposition of the material.

Abstract: A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit comprises a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge, operatively coupled to the SOI MOSFET. A first determination is made of the effects of an uncontrolled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide of the SOI MOSFET. A second determination is made of the effects of a controlled accumulated charge on TDDB of the gate oxide of the SOI MOSFET.

Abstract: A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.

Abstract: A silicon-on-insulator metal oxide semiconductor device comprising ultrathin silicon-on-sapphire substrate; at least one P-channel MOS transistor formed in the ultrathin silicon layer; and N-type impurity implanted within the ultrathin silicon layer and the sapphire substrate such that peak N-type impurity concentration in the sapphire layer is greater than peak impurity concentration in the ultrathin silicon layer.

Abstract: In an arrangement for generating a local electron-cyclotron-microwave-low pressure plasma at a certain location within a gas-filled process chamber, a microwave supply means providing a microwave beam and a plasma localization unit generating a magnetic field are provided such that the magnetic field and the microwave beam intersect each other in the process chamber. The microwaves are uncoupled onto a concave reflection structure from the focal point thereof so that the microwave beam generated is essentially parallel. An arrangement for generating a magnetic field is movable along the microwave beam axis so that a cross volume between the microwave beam and the magnetic field can be moved along the beam axis whereby the conditions for electron cyclotron resonance are adjustable by displacement of the magnetic field.

Abstract: A method for eliminating the radiation-induced off-state current in the P-channel ultrathin silicon-on-sapphire transistor, by providing a retrograde dopant concentration profile that has the effect of moving the Fermi level at the back of the device away from that part of the bandgap where the interface states are located. When the Fermi level does not swing through this area in any region of operation of the device, subthreshold stretchout of the I-V curves does not occur.

Abstract: An integrated photodetector means for controlling the output of a light source, where the control means is a photodetector formed on a silicon-on-insulator substrate. The integrated photodetector senses the optical power from the light source and provides an electrical feedback signal which can be used to adjust the DC bias levels of the light source control driver circuit. The approach readily lends itself to large arrays of light sources bonded to silicon-on-sapphire driver circuits and is especially suitable for controlling light sources such as VCSELs in arrays such as are found in communications systems.

Abstract: A method for eliminating the radiation-induced off-state current in the P-channel ultrathin silicon-on-sapphire transistor, by providing a retrograde dopant concentration profile that has the effect of moving the Fermi level at the back of the device away from that part of the bandgap where the interface states are located. When the Fermi level does not swing through this area in any region of operation of the device, subthreshold stretchout of the I-V curves does not occur.

Abstract: A method for eliminating the radiation-induced off-state current in the P-channel ultrathin silicon-on-sapphire transistor, by providing a retrograde dopant concentration profile that has the effect of moving the Fermi level at the back of the device away from that part of the bandgap where the interface states are located. When the Fermi level does not swing through this area in any region of operation of the device, subthreshold stretchout of the I-V curves does not occur.

Abstract: In a method of manufacturing a composite material structure consisting of a substrate with a layer of essentially pure sp.sup.2 - and sp.sup.3 -hybridized carbon with a sp.sup.3 -hybridized carbon proportion which increases toward the surface of the carbon layer, the carbon layer is deposited on the substrate by a PVD process using a magnetron sputtering apparatus in a process chamber in which an argon partial pressure of 0.6 to 1.0 pa is maintained and, during the carbon deposition, a bias voltage is maintained which is increased with increasing thickness of the layer from 0 to 300 volts.

Abstract: An LDD field effect transistor is fabricated by a series of process steps in which throughout the fabrication process, the transistor's polysilicon gate is protected from being oxidized on its edges near the gate insulator. Some of the process steps during which the above protection occurs includes steps for forming spacers on the sidewalls of the transistor's gate, and steps for activating the LDD source-drain regions with high temperature anneals. Due to this protection from oxidation, none of the silicon in the edges of the gate is consumed or converted to silicon dioxide at any stage of the fabrication process. Consequently, the distance by which the edges of the gate are spaced over the channel remains unaltered throughout the fabrication process; and, this physical feature of the gate makes the transistor's saturation current large with little variance.