Abstract: A processor 2 is responsive to a stream of program instructions to issue program instructions under control of scheduling circuitry 6 to respective execution units 24 for execution. The execution units 24 can include error detecting circuitry 32 for detecting a change in an output signal which occurs after the output signal has latched and during an error detecting period following the latching of the output signal. The scheduling circuitry 6 is arranged so as to suppress issue of program instructions to an execution unit 24 having such error detecting circuitry 32 on consecutive processing cycles.

Abstract: A data processing apparatus is provided comprising processing circuitry for executing multiple program threads. At least one storage unit is shared between the multiple program threads and comprises multiple entries, each entry for storing a storage item either associated with a high priority program thread or a lower priority program thread. A history storage for retaining a history field for each of a plurality of blocks of the storage unit is also provided. On detection of a high priority storage item being evicted from the storage unit as a result of allocation to that entry of a lower priority storage item, the history field for the block containing that entry is populated with an indication of the evicted high priority storage item.

Abstract: A method and integrated circuit for accessing data in a pipelined data processing apparatus in which the operating conditions of the pipelined data processing apparatus are such that metastable signals may occur on at least the boundaries of the pipelined stages is disclosed.

Abstract: To prevent short path errors from occurring in systems having error detection and recovery mechanisms, functional elements are combined to form compound functional units comprising at least two evaluation stages, each evaluation stage including at least one functional element. At least one functional element includes error detection/recovery circuitry. The flow of input values to the first evaluation stage in the compound functional unit is controlled so that the input values are changed at most every second clock cycle.

Abstract: A circuit for a data processing apparatus and a method for detecting spurious signals is disclosed, the circuit comprising a data input operable to receive digital signal values, spurious signal detection logic operable to monitor a digital signal value within the circuit, and to determine at least one of: a safe time window during which it is expected that the digital signal values input into the circuit may cause data transitions in the monitored digital signal value and a transition time window in which it is expected a data transition will occur; and in response to detecting either a data transition in the monitored digital signal value outside of the at least one safe time window or no data transition in the transition window, the spurious signal detection logic is operable to output a detection signal.

Abstract: A data processing system comprising a memory array having a plurality of memory cells (240-246) and read circuitry (310,320) for reading a logic value stored in one of the plurality of memory cells. The read circuitry (310,320) is operable perform two substantially simultaneous reads of the stored logic value. A voltage controller is provided and is operable to selectively vary a level of a supply voltage to the memory array. Detection circuitry is provided (330) for detecting, in dependence upon the two substantially simultaneous reads, when the supply voltage level causes the read result to be unreliable.

Abstract: An integrated circuit 2 is provided with a plurality of pipeline stages 10. These pipeline stages 10 have speculative processing control circuitry 12 which permits speculative processing in downstream pipeline stages and triggers a first error recovery operation (partial pipeline flushing) if such speculative processing is determined to be based upon an error. The pipeline stage 10 further includes speculative error detecting circuitry 14 which generates a prediction nc regarding whether or not the processing circuitry 18 will produce an error. This prediction is used to trigger a second error recovery operation (partial pipeline stall). This second error recovery operation has a lower performance penalty than the first error recovery operation.

Abstract: An instruction processing pipeline 6 is provided. This has error detection and error recovery circuitry 20 associated with one or more of the pipeline stages. If an error is detected within a signal value within that pipeline stage, then it can be repaired. Part of the error recovery may be to flush upstream program instructions from the instruction pipeline 6. When multi-threading, only those instructions from a thread including an instruction which has been lost as a consequence of the error recovery need to be flushed from the instruction pipeline 6. Instruction can also be selected for flushing in dependence upon characteristics such as privileged level, number of dependent instructions etc.

Abstract: A method and integrated circuit for accessing data in a pipelined data processing apparatus in which the operating conditions of the pipelined data processing apparatus are such that metastable signals may occur on at least the boundaries of the pipelined stages is disclosed.

Abstract: A circuit for a data processing apparatus is disclosed, said circuit comprising a data input operable to receive digital signal values, said circuit comprising: spurious signal detection logic operable to monitor a digital signal value within said circuit, and determine at least one of: a safe time window during which it is expected that said digital signal values input into said circuit may cause data transitions in said monitored digital signal value and a transition time window in which it is expected a data transition will occur; and in response to detecting either a data transition in said monitored digital signal value outside of said at least one safe time window or no data transition in said transition window, said spurious signal detection logic is operable to output a detection signal.

Abstract: An integrated circuit 2 includes processing pipeline stages formed of an input register 8, processing circuit 10?, 10? and an output register 12. The output register 12 employs speculative sampling and uses a subsequent speculation period during which any change in its input is detected and used to indicate a speculation error. In order to reduce the chances of a race condition giving rise to a false positive detection of a speculation error due to a too rapid signal propagation through the processing circuitry 10?, 10?, a transparent latch 14 is disposed at the approximate midpoint, measured in terms of propagation delay, within the processing circuitry 10?, 10?. This transparent latch 14 is non-transmissive during the speculation period of the output register 12 so as to prevent any new signal propagating from the input register 8 during the speculation period from reaching the output register 12.

Abstract: A multi-layered pipe includes at least an outer and an inner layer of thermoplastic material and a coupling comprising a thermoplastic material. A method for joining the multi-layered pipe to the coupling includes providing a coupling including a recess for receiving an end of a multi-layered pipe, the recess being configured, in use, to permit the coupling to contact the inner and outermost layers of a multi-layered pipe received in the recess; fitting an end of the multi-layered pipe into the recess R of the coupling; introducing heat to both the coupling sufficient to cause local melting at the interface between the coupling and either the inner layer alone or both the inner and outer layers of the multi-layered pipe.

Abstract: A multi-layered pipe includes at least an outer and an inner layer of thermoplastic material and a coupling includes a thermoplastic material. A method for joining the pipe to the coupling includes providing a coupling including a recess for receiving an end of a multi-layered pipe, the recess being configured, in use, to permit the coupling to contact the inner and outermost layers of a multi-layered pipe received in the recess. An end of the multi-layered pipe is fit into the recess of the coupling. Heat is introduced to both the coupling sufficient to cause local melting at the interface between the coupling and either the inner layer alone or both the inner and outer layers of the multi-layered pipe.

Abstract: An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014. An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024. The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value.

Abstract: A method of producing a clad sheet article having superplastic properties, and the resulting clad sheet article. The method involves producing a cladding layer onto at least one rolling face of a core ingot made of a metal having superplastic properties, preferably by co-casting, to form a clad ingot and then rolling said clad ingot to produce a sheet article. The core ingot includes an element that diffuses from an interior of the ingot to a surface at superplastic forming temperatures thereby deteriorating surface properties of the ingot. The cladding layer is provided with an element (dopant) that reacts with the element of the core to reduce the ability of the element to diffuse through the cladding layer.

Abstract: A memory circuit is provided comprising a memory cell, a pair of conducting lines operable to signal the logic state of the memory cell and read circuitry operable to perform a read operation by detecting a voltage level of at least one of the pair of conducting lines. The memory circuit comprises a pull-down circuit having an on configuration in which it is operable to pull-down a voltage level of at least one of the pair of conducting lines so as to affect the read operation and an off-configuration in which the pull-down circuit cannot affect the read operation. Control circuitry is provided to control whether the pull-down circuit is in the on configuration or the off configuration. The memory circuit can be incorporated in a data processing apparatus and a method of operating a memory circuit is provided in which a pull-down circuit is controlled to be in an on configuration or in an off configuration.

Abstract: A method for joining a multi-layered pipe to a coupling, the multi-layered pipe including at least an outer and an inner layer of thermoplastic material and the coupling including a thermoplastic material. The method includes providing a coupling including a recess for receiving an end of a multi-layered pipe, the recess being configured, in use, to permit the coupling to contact the inner and outermost layers of a multi-layered pipe received in the recess. An end of the multi-layered pipe is fit into the recess of the coupling. Heat is introduced to both the coupling sufficient to cause local melting at the interface between the coupling and either the inner layer alone or both the inner and outer layers of the multi-layered pipe.

Abstract: A signal capture element for providing a first pre-charged logic level as first and second interim address portion signals during a pre-charged period and outputting during an evaluate period an address portion logic level as the first interim address portion signal and an inverted address portion logic level as the second interim address portion signal. First and second address portion signals are derivable respectively from first and second interim address portion signals. An inverter circuit for outputting to an address decoder during a pre-charged period a second pre-charged logic level as the first and second address portion signals. The inverter circuit having transfer characteristics that maintain voltage levels such that the first and second address portion signals are interpreted to be at the second pre-charged logic level despite the first or second interim address portion signal failing to transition to a valid logic level during the evaluate period.

Abstract: A memory for storing data comprising a fast data reading mechanism operable to sense one or more signal values dependent upon a data value stored in said memory so as to generate a first signal transition indicative of said data value and used to generate a fast read result that is output from said memory for further processing; a slow data reading mechanism operable to sense said one or more signal values dependent upon said data value so as to generate a second signal transition indicative of said data value and used to generate a slow read result available after said fast read result, said slow read result being less prone to error than said fast read result; a comparator operable to compare said fast read result and said slow read result and to generate an error signal if said fast read result does not match said slow read result; and a timing checker coupled to said fast data reading mechanism and operable to detect that said first signal transition was generated within a predetermined time and generate

Abstract: A method and apparatus for the casting of a composite metal ingot comprising at least two separately formed layers of one or more alloys. An open ended annular mould has a feed end and an exit end and divider wall for dividing the feed end into at least two separate feed chambers, where each feed chamber is adjacent at least one other feed chamber. For each pair of adjacent feed chambers a first alloy stream is fed through one of the pair of feed chambers into the mould and a second alloy stream is fed through another of the feed chambers.