Abstract: The present invention relates to a technique for accessing memory units in a data processing apparatus. The data processing apparatus comprises of plurality of memory units for storing data values, a processor core for issuing an access request specifying an access to be made to the memory units in relation to a data value, and a memory controller for performing the access specified by the access request. Attribute generation logic is provided for determining from the access request one or more predetermined attributes verifying which of the memory units should be used when performing the access. However, the memory controller does not wait until such determination has been performed by the attribute generation logic before beginning the access.

Abstract: A memory circuit 2 includes a plurality of memory cells 4, 6 which are subject to memory access operations. These memory access operations serve to selectively discharge one or more of the bit lines A, Abar, B, Bbar associated with the memory cells 4, 6. During a subsequent precharge operation serving to restore the precharged voltage levels of the bit lines A, Abar, B Bbar charge sharing is performed between non-accessed bit lines and those which have been accessed and accordingly at least partially discharged. Also the precharging circuits 12, 14, 16, 18 associated with the non-accessed bit lines contribute towards the precharging operation.

Abstract: A valid memory 2 is provided storing valid words 8 with bit positions indicating whether corresponding cache lines within a cache memory 7 store valid data. Flip-flop circuits 4 are provided to indicate whether or not the valid words 8 within the valid memory 2 are themselves valid. The number of valid words 8 corresponding to an individual flip-flop circuit 4 varies in dependence upon the size of the valid memory 2. Thus, for example, a single flip-flop circuit 4 may indicate whether one, two, four or eight valid words 8 from the valid memory 2 are storing valid data depending upon the particular size of the valid memory 2 employed.

Abstract: A valid memory 2 is provided storing valid words 8 with bit positions indicating whether corresponding cache lines within a cache memory 7 store valid data. Flip-flop circuits 4 are provided to indicate whether or not the valid words 8 within the valid memory 2 are themselves valid. The number of valid words 8 corresponding to an individual flip-flop circuit 4 varies in dependence upon the size of the valid memory 2. Thus, for example, a single flip-flop circuit 4 may indicate whether one, two, four or eight valid words 8 from the valid memory 2 are storing valid data depending upon the particular size of the valid memory 2 employed.

Abstract: A valid memory 2 is provided storing valid words 8 with bit positions indicating whether corresponding cache lines within a cache memory 7 store valid data. Flip-flop circuits 4 are provided to indicate whether or not the valid words 8 within the valid memory 2 are themselves valid. The number of valid words 8 corresponding to an individual flip-flop circuit 4 varies in dependence upon the size of the valid memory 2. Thus, for example, a single flip-flop circuit 4 may indicate whether one, two, four or eight valid words 8 from the valid memory 2 are storing valid data depending upon the particular size of the valid memory 2 employed.

Abstract: An aluminium alloy in the AA5XXX series has the composition: Si 0.10-0.25 %; Fe 0.18-0.30 %; Cu up to 0.5 %; Mn 0.4-0.7 %; Mg 3.0-3.5%; Cr up to 0.2%; and Ti up to 0.1%. Rolled and annealed sheet of the alloy is readily formed into shaped components for use in vehicles which components have good strength and resistance to stress corrosion cracking.

Abstract: A data processing system is provided having a main processor 4 and a coprocessor 26. When in a debug mode, the main processor 4 and the coprocessor 26 are supplied with different instructions. The coprocessor 26 is supplied with a coprocessor debug data generation instruction (MCR) whilst the main processor 4 is supplied with a main processor data capture instruction (LDR). The coprocessor 26 responds to the MCR instruction by controlling debug data representing state of the data processing apparatus 2 to be placed upon a data bus 24 from where it is read by the main processor 4 under control of the LDR instruction.

Abstract: The present invention relates to a technique for accessing memory units in a data processing apparatus. The data processing apparatus comprises of plurality of memory units for storing data values, a processor core for issuing an access request specifying an access to be made to the memory units in relation to a data value, and a memory controller for performing the access specified by the access request. Attribute generation logic is provided for determining from the access request one or more predetermined attributes verifying which of the memory units should be used when performing the access. However, the memory controller does not wait until such determination has been performed by the attribute generation logic before beginning the access.

Abstract: A data processing system 2 is provided with a processor core 4 that issues virtual addresses VA that are translated to mapped addresses MA by an address translation circuit 6 based upon a predicted address mapping. The mapped address MA is used for a memory access within a memory system 8. The mapped address MA starts to be used before a mapping validity circuit 6 has determined whether or not the predicted translation was valid. Accordingly, if the predicted address translation turns out to be invalid, then the memory access is aborted. The state of the processor core is preserved either by stretching the processor clock signal or by continuing the processor clock signal and waiting the processor 4. The memory system 8 then restarts the memory access with the correct translated address.

Abstract: A decoder is provided for generating N output signals, the decoder comprising a precharged gate structure arranged to receive two or more input signals and to generate N intermediate signals. In a precharge phase, the precharged gate structure is arranged to output the N intermediate signals at a first logic value, and in an evaluate phase the precharged gate structure is arranged to maintain a first intermediate signal at the first logic value, and to cause all other intermediate signals to transition to a second logic value. Further, self-timed logic is provided for receiving the N intermediate signals, and for generating the N output signals, the self-timed logic being arranged, during the precharge phase, to generate the N output signals at the second logic value, and during the evaluate phase to cause a first output signal corresponding to the first intermediate signal to transition to the first logic value.

Abstract: A digital logic simulation system simulates a digital logic system having component blocks connected by nets with a master queue that contains events to be performed during the simulation, a scheduler that adds events to the master queue such that the processing of each block is represented by an update event and a compute event, and a dispatcher that maintains a time clock that defines a simulation clock time, extracts events from the master queue according to the simulation clock time, and produces a simulation output, such that wire delays for particular nets are modelled with a corresponding update event and compute event. Only those nets that have an associated wire delay that is being modelled will cause a wire delay update event and compute event. All other nets will not result in wire delay events.