Abstract: A circuit and method provide a charge sharing function during skewed data bus conditions in an integrated circuit memory. The charge sharing circuit includes two additional circuit blocks, one coupled to each of the capacitive lines in the charge-sharing line set, to provide the charge recycling feature. An extra clock signal is active one cycle early during a first clock period to trigger an extra drive circuit to generate a voltage differential on a first capacitive line that is similar to the voltage level generated when real data is being propagated. The presence of an extra voltage signal on the first capacitive line takes place earlier than what would normally happen and allows for proper charge sharing between a second capacitive line and the first capacitive line. Also, there is an additional control signal associated with a last clock period following normal non-skewed charge sharing.

Abstract: A twin cell architecture for dynamic random access memory (DRAM) devices and those devices incorporating embedded DRAM utilizing an open bitline configuration is disclosed. The twin cell architecture disclosed has significant advantages over conventional designs in terms of power, radiation hardness and speed and does not require intermediate supply voltage bitline precharge while allowing for 6F2 memory cell layouts.

Abstract: A clock distribution tree for an integrated circuit memory includes a set of data drivers, a corresponding set of input buffers coupled to the data drivers, a first clock distribution tree coupled to the data drivers, and a second clock distribution tree coupled to the input buffers, wherein the first and second clock distribution tree are substantially matched and mirrored distribution trees. The line width of the first clock distribution tree is substantially the same as the line width of the second clock distribution tree. The line spacing of the first clock distribution tree is substantially the same as the line spacing of the second clock distribution tree. Numerous topologies for the first and second clock distribution trees can be accommodated, as long as they are matched and mirrored. Valid times for the integrated circuit memory are maximized and data and clock skew is minimized.

Abstract: A charge-sharing circuit includes a first input bus pair, a second input bus pair, and an output bus pair. A capacitor is coupled between a first internal node and a second internal node. A first circuit selectively couples the first internal node to the first input bus pair, the second input bus pair and the output bus pair. A second circuit selectively couples the second internal node to the first input bus pair, the second input bus pair and the output bus pair. A third circuit selectively couples the first input bus pair to a reference voltage. A fourth circuit selectively couples the second input bus pair to the reference voltage. The third circuit is activated when the first input bus pair is inactive and charge is shared between the second bus pair and the output bus pair. The fourth circuit is activated when the second input bus pair is inactive and charge is shared between first bus pair and the output bus pair.

Abstract: A high-speed, static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a data cache and separate data read and write registers and tag blocks. The inclusion of separate data read and write registers allows the device to effectively operate at a cycle time limited only by the DRAM subarray cycle time. Further, the inclusion of two tag blocks allows one to be accessed with an externally supplied address and the other to be accessed with a write-back address, thus eliminating the requirement for a single tag to execute two read-modify write cycles in one DRAM cycle time.

Abstract: A data inversion register technique for integrated circuit memory testing in which data input signals are selectively inverted in a predetermined pattern to maximize the probability of identifying failures during testing. In accordance with the technique of the present invention, on predetermined input/outputs (I/Os,) data inputs may be inverted to create a desired test pattern (such as data stripes) which are “worst case” for I/O circuitry or column stripes which are “worst case” for memory arrays. A circuit in accordance with the technique of the present invention then matches the pattern for the data out path, inverting the appropriate data outputs to obtain the expected tester data. In this way, the test mode is transparent to any memory tester.

Abstract: A short-circuit charge-sharing technique which allows charge-sharing between two or more circuits with a simple shorting transistor controlled to achieve the desired operating voltage levels. The shorting transistor which can be either a P-channel Metal Oxide Semiconductor (PMOS) or an N-channel Metal Oxide Semiconductor (NMOS) device and can be controlled utilizing the same clock that enables the drive of the signals between which charge-sharing occurs. In operation, the desired operating voltage levels can be regulated by increasing and decreasing the pulse width of the control circuit output to the gate of the shorting transistor.

Abstract: An early write with data masking technique for dynamic random access memory (DRAM) devices and those devices incorporating embedded DRAM. The technique of the present invention allows for early writes to DRAM arrays with direct bit, byte or word data masking capability.

Abstract: A high-speed, static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a data cache and separate data read and write registers and tag blocks. The inclusion of separate data read and write registers allows the device to effectively operate at a cycle time limited only by the DRAM subarray cycle time. Further, the inclusion of two tag blocks allows one to be accessed with an externally supplied address and the other to be accessed with a write-back address, thus eliminating the requirement for a single tag to execute two read-modify write cycles in one DRAM cycle time.

Abstract: An ECC circuit and method for an integrated circuit memory allows a user to enter a test mode and select a specific location to force a known failure on any memory chip, whether it is fully functional or partially functional. Additional circuitry is placed in the data path where existing buffers and drivers are already located, minimizing any additional speed loss or area penalty required to implement the forced data failure. In a first general method, a logic zero is forced onto a selected data line at a given time. In a second general method, a logic one is forced onto a selected data line at a given time.

Abstract: A clock distribution tree for an integrated circuit memory includes a set of data drivers, a corresponding set of input buffers coupled to the data drivers, a first clock distribution tree coupled to the data drivers, and a second clock distribution tree coupled to the input buffers, wherein the first and second clock distribution tree are substantially matched and mirrored distribution trees. The line width of the first clock distribution tree is substantially the same as the line width of the second clock distribution tree. The line spacing of the first clock distribution tree is substantially the same as the line spacing of the second clock distribution tree. Numerous topologies for the first and second clock distribution trees can be accommodated, as long as they are matched and mirrored. Valid times for the integrated circuit memory are maximized and data and clock skew is minimized.

Abstract: A charge-sharing circuit includes a first input bus pair, a second input bus pair, and an output bus pair. A capacitor is coupled between a first internal node and a second internal node. A first circuit selectively couples the first internal node to the first input bus pair, the second input bus pair and the output bus pair. A second circuit selectively couples the second internal node to the first input bus pair, the second input bus pair and the output bus pair. A third circuit selectively couples the first input bus pair to a reference voltage. A fourth circuit selectively couples the second input bus pair to the reference voltage. The third circuit is activated when the first input bus pair is inactive and charge is shared between the second bus pair and the output bus pair. The fourth circuit is activated when the second input bus pair is inactive and charge is shared between first bus pair and the output bus pair.

Abstract: A data bus charge-sharing technique for integrated circuit devices may be implemented utilizing two voltage regulators to generate constant voltages VEQ1 and VEQ2, which are in the particular exemplary implementation disclosed, approximately 0.9 times a supply voltage VCC and 0.1 times VCC, respectively. One set of signals switches between VCC and VEQ1, and a second set of signals switches between VEQ2 and 0V. Charge-sharing between the two sets of signals is accomplished by the unique configuration of the voltage regulators.

Abstract: A circuit and method provide a charge sharing function during skewed data bus conditions in an integrated circuit memory. The charge sharing circuit includes two additional circuit blocks, one coupled to each of the capacitive lines in the charge-sharing line set, to provide the charge recycling feature. An extra clock signal is active one cycle early during a first clock period to trigger an extra drive circuit to generate a voltage differential on a first capacitive line that is similar to the voltage level generated when real data is being propagated. The presence of an extra voltage signal on the first capacitive line takes place earlier than what would normally happen and allows for proper charge sharing between a second capacitive line and the first capacitive line. Also, there is an additional control signal associated with a last clock period following normal non-skewed charge sharing.

Abstract: A switched capacitor charge sharing technique for integrated circuit devices which allows for efficient charge sharing and signal level generation of exact desired values, and wherein the signal levels of the circuits sharing the charge do not have to have the same voltage levels. In a particular embodiment of the technique of the present invention disclosed herein, a switched capacitor is used to share charge between, for example, two different signals or two different groups of signals. The size of the capacitor can be adjusted to obtain the required signal level of the various signals.

Abstract: A layout area efficient, high speed, dynamic multi-input exclusive OR (XOR) and exclusive NOR (XNOR) logic gate circuit design of especial utility with respect to integrated circuit devices. The logic gate design disclosed herein utilizes fewer transistors than traditional static designs and, therefore, requires a smaller amount of integrated circuit layout area while nevertheless affording higher speed operating performance than that exhibited in existing conventional circuits.

Abstract: A powergating circuit includes a P-channel transistor with a source coupled to VCC, a gate for receiving a first boosted or non-boosted powergating control signal, and a drain forming the internal switched VCC power supply. An N-channel transistor has a source coupled to VSS, a gate for receiving a second boosted or non-boosted powergating control signal, and a drain forming the internal switched VSS power supply. The powergating circuit further includes a circuit for forcing the first and second internal power supply voltages to a mid-point reference voltage during the standby mode.

Abstract: A reduced gate delay multiplexed interface and output buffer circuit for random access memory arrays, such as synchronous dynamic random access memory (“SDRAM”) devices, or other integrated circuit devices incorporating embedded memory arrays which reduces data access time and clock latency. In accordance with the present invention, data is multiplexed (or selected) and driven out at the memory bank level rather than at the output pad area (or the embedded RAM macro edge) as in prior art techniques.

Abstract: A precharge initiated dynamic random access memory (DRAM) technique of especial utility with respect to DRAM devices and other integrated circuit devices incorporating embedded DRAM in which the rising edge of each clock initiates a precharge to those subarrays that were active as opposed to conventional techniques wherein the subarrays are typically precharged so that they are made ready on the rising edge of the clock, which would then start an active cycle. The longer restore time that is achieved can be used to enable the establishment of better logic “1” and “0” levels in the memory cells, to reduce the device clock period and/or to enable other functions to be performed in parallel with the precharge function.

Abstract: A dual access DRAM includes first and second sets of data lines. By adding a second set of multiplexing transistors to data lines that are controlled with timing and addressing similar to an existing set of multiplexing transistors, data can be transferred to a second subarray by way of an additional set of data lines. The second set of data lines are additional internal read/write lines used in addition to the normal set of data lines. The second set of data lines are designed to have short lengths with correspondingly low capacitance so that additional loading on the sense amplifiers is small.