Abstract: A low power Sleep Mode operation technique for dynamic random access (DRAM) devices and integrated circuit devices incorporating embedded DRAM. By counting clock (CLK) cycles in accordance with the technique disclosed, refresh time (tREF) does not vary with all possible process corners, voltages and temperatures (PVT) since the clock signal exhibits a steady frequency over PVT applied to the DRAM and an internal timer placed on chip will vary directly with these parameters. After entering Sleep Mode, the main internal clock signal is inhibited from propagating around the device chip and, at this time, much of the associated circuitry can be power-gated to conserve power, typically with signals that have a boosted level to provide a negative gate-to-source voltage (VGS) on the power-gating transistors.

Abstract: A powergating circuit includes an MOS circuit such as a memory circuit having a first power terminal and a second power terminal, a P-channel transistor having a drain coupled to the first power terminal of the MOS circuit, and an N-channel transistor having a drain coupled to the second power terminal of the MOS circuit. In order to minimize leakage current and resultant power dissipation a negative VGS voltage is established in the transistors during a standby mode and a boosted VGS voltage is established in the transistors during an active mode.

Abstract: An integrated circuit memory includes circuitry for individually activating word lines in a first one memory cell per bit operational mode, simultaneously activating at least two word lines in a second operational mode where two or more memory cells are dedicated to each data bit, and providing a word line sequence when first converting stored data in the array of memory cells from the first operational mode to the second operational mode. The word line sequence includes activating a first word line, developing a valid signal on a corresponding bit line, and then activating a second word line while the first word line is still active.

Abstract: A low power Sleep Mode operation technique for dynamic random access (DRAM) devices and integrated circuit devices incorporating embedded DRAM. By counting clock (CLK) cycles in accordance with the technique disclosed, refresh time (tREF) does not vary with all possible process corners, voltages and temperatures (PVT) since the clock signal exhibits a steady frequency over PVT applied to the DRAM and an internal timer placed on chip will vary directly with these parameters. After entering Sleep Mode, the main internal clock signal is inhibited from propagating around the device chip and, at this time, much of the associated circuitry can be power-gated to conserve power, typically with signals that have a boosted level to provide a negative gate-to-source voltage (VGS) on the power-gating transistors.

Abstract: A refresh circuit is used for refreshing or masking from refresh non-contiguous subarrays in an integrated circuit memory array. At the initiation of each masked refresh cycle the address inputs, which normally are ignored, are evaluated to indicate which subarrays should be refreshed and which should be not refreshed. Power is saved due to the flexibility in determining which subarrays are refreshed at each new refresh cycle.

Abstract: A refresh circuit is used for refreshing or masking from refresh non-contiguous subarrays in an integrated circuit memory array. At the initiation of each masked refresh cycle the address inputs, which normally are ignored, are evaluated to indicate which subarrays should be refreshed and which should be not refreshed. Power is saved due to the flexibility in determining which subarrays are refreshed at each new refresh cycle.

Abstract: A bitline reference voltage circuit according to the present invention includes a first transistor having a current path coupled between a first bitline and an intermediate node, and a gate for receiving a first control signal, a second transistor having a current path coupled between a second bitline and the intermediate node, and a gate for receiving a second control signal, a third transistor having current path coupled between the intermediate node and a source of constant voltage, and a gate for receiving a third control signal, and a capacitor coupled between the intermediate node and the source of constant voltage.

Abstract: A bitline reference voltage circuit according to the present invention includes a first transistor having a current path coupled between a first bitline and an intermediate node, and a gate for receiving a first control signal, a second transistor having a current path coupled between a second bitline and the intermediate node, and a gate for receiving a second control signal, a third transistor having current path coupled between the intermediate node and a source of constant voltage, and a gate for receiving a third control signal, and a capacitor coupled between the intermediate node and the source of constant voltage.

Abstract: A reduced gate delay multiplexed interface and output buffer circuit for random access memory arrays, such as synchronous dynamic random access memory (“SDRAM”) devices, or other integrated circuit devices incorporating embedded memory arrays which reduces data access time and clock latency. In accordance with the present invention, data is multiplexed (or selected) and driven out at the memory bank level rather than at the output pad area (or the embedded RAM macro edge) as in prior art techniques.

Abstract: A powergating circuit includes an MOS circuit such as a memory circuit having a first power terminal and a second power terminal, a P-channel transistor having a drain coupled to the first power terminal of the MOS circuit, and an N-channel transistor having a drain coupled to the second power terminal of the MOS circuit. In order to minimize leakage current and resultant power dissipation a negative VGS voltage is established in the transistors during a standby mode and a boosted VGS voltage is established in the transistors during an active mode.

Abstract: A non-clocked data-in path in an integrated circuit device incorporating a random access memory array allows data written to the array to ripple through to all banks all the way up to the local write circuitry. This allows for the fastest writes possible to the array since there are no additional clocking registers to slow down the data flow.

Abstract: An optimized read data amplifier for the output data path of integrated circuit memory arrays comprises a fast, low power and small on-chip area consuming circuit which is advantageously effectuated through the combined application of “current sensing” and “voltage sensing” techniques. In a particular embodiment disclosed herein, an amplifier enable signal is timed with the column read address so that the amplifier is turned “off” when not in use and both data read lines (“DR” and “DRB”) are precharged “high”. No clocking of the read data amplifier is required in order to obviate undesired clock latencies and pipelining and a simple mechanism is implemented such that control of power-up and power-down results in further power savings.

Abstract: A non-clocked data-in path in an integrated circuit device incorporating a random access memory array allows data written to the array to ripple through to all banks all the way up to the local write circuitry. This allows for the fastest writes possible to the array since there are no additional clocking registers to slow down the data flow.

Abstract: An integrated and constantly enabled on-chip test interface for use in verifying the functionality of high speed embedded memories such as synchronous dynamic random access memories (“SDRAM”) which allows for the utilization of existing, relatively low speed, (and hence low cost), testers to perform the testing. The interface allows for the verification of an embedded memory macro design utilizing a test interface which includes the memory macro and separate on-chip test circuitry so that half-rate, narrow word, input signals from a tester can perform all memory macro operations across the breadth of a wide memory macro input/output (“I/O”) architecture. The on-chip test circuitry may also include a synchronizing circuit to minimize skew between the external clock and the data output from the test chip.

Abstract: A high voltage transistor protection technique and switching circuit of especial applicability to integrated circuit devices utilizing multiple power supply voltages. In accordance with the technique of the present intention, the problems inherent in the amount of on-chip die area consumed and speed degradation of prior art circuit implementations are overcome by furnishing a substantially direct current voltage VHVP to the gate of a first transistor of a series connected thin gate oxide pair wherein VHVP≦VDSMAX (the maximum gate-to-source voltage of the first transistor) and VHVP≦VDSMAX+Vt (the maximum drain-to-source voltage of the second transistor plus the threshold voltage of the first transistor).

Abstract: A time data compression technique which allows high speed integrated circuit (“IC”) memory devices to be tested at full speed with test equipment which is capable of operating at only at relatively slower speeds than that of the memory devices without increasing test time or decreasing production throughput. Through the use of the technique disclosed herein, data is initially sorted in time and them compared for a predetermined number of logic level “1s” or “0s” to be effectively compressed in time. This time compression allows high rate data streams to be tested at effectively slower rates. The technique of the present invention can be utilized to effectively reduce the data rate by one half, one quarter or to any sub-multiple of the normal memory frequency without increasing time in test.

Abstract: A system and method for low cost testing of integrated circuit devices at their rated speed during wafer probe testing while input signals to, and output signals from, the device may be operated at a lower speed. In the exemplary embodiment disclosed, a probe pad is used to enable a special test mode. When enabled, the on-chip clock generator enables a clock frequency doubler. The frequency doubler generates a 2× frequency clock from the 1× frequency external clock signals (two 1× clock phases with a 90 degree phase shift between the two clocks). The first phase of the clock uses the CLK input of the device and the second phase uses the device's CKE input.

Abstract: A simultaneous function dynamic random access memory (“DRAM”) technique of particular applicability to DRAMs, synchronous DRAMs (“SDRAM”), specialty DRAMs, embedded DRAMs, embedded SDRAMs and the like which enables the execution of “read”, “write”, “active” and “precharge” commands on a single clock cycle. The technique of the present invention is of especial applicability to embedded memory arrays or specialty DRAMs where the number of input signals to the DRAM are not necessarily limited by mechanical component packaging constraints or component pin counts. In general, the advantages of the technique are obtained through the use of separate address fields, including bank addresses, for “read” and “write” commands, and separate bank addresses for “active” and “precharge” commands with a resultant highly parallel operational functionality.

Abstract: A simultaneous function dynamic random access memory (“DRAM”) technique of particular applicability to DRAMs, synchronous DRAMs (“DRAM”), specialty DRAMs, embedded DRAMs, embedded SDRAMs and the like which enables the execution of “read”, “write”, “active” and “precharge” commands on a single clock cycle. The technique of the present invention is of especial applicability to embedded memory arrays or specialty DRAMs where the number of input signals to the DRAM are not necessarily limited by mechanical component packaging constraints or component pin counts. In general, the advantages of the technique are obtained through the use of separate address fields, including bank addresses, for “read” and “write” commands, and separate bank addresses for “active” and “precharge” commands with a resultant highly parallel operational functionality.

Abstract: A data path decoding technique and architecture for integrated circuit memory devices and those devices incorporating embedded dynamic random access memory (“DRAM”) arrays provides an effective second level of decoding resulting in a need for routing fewer column select lines to the sense amplifiers as compared with existing designs while concomitantly providing for shortened local data lines resulting in less undesired resistance and capacitance. The technique and architecture of the present invention requires no additional on-chip area to that required by existing designs and adds no new gate delays or pass gates to the critical read data or write data paths. This is effectuated by the incorporation of an address function with the read/write enable (“RWEN”) or separate read enable (“REN”) and write enable (“WEN”) signals. Consequently, half as many column select lines need be routed to the sense amplifiers since a second level of column decoding is provided.