Abstract: A data path decoding technique and architecture for integrated circuit memory devices and those devices incorporating embedded dynamic random access memory (“DRAM”) arrays provides an effective second level of decoding resulting in a need for routing fewer column select lines to the sense amplifiers as compared with existing designs while concomitantly providing for shortened local data lines resulting in less undesired resistance and capacitance. The technique and architecture of the present invention requires no additional on-chip area to that required by existing designs and adds no new gate delays or pass gates to the critical read data or write data paths. This is effectuated by the incorporation of an address function with the read/write enable (“RWEN”) or separate read enable (“REN”) and write enable (“WEN”) signals. Consequently, half as many column select lines need be routed to the sense amplifiers since a second level of column decoding is provided.

Abstract: A data path decoding technique and architecture for integrated circuit memory devices and those devices incorporating embedded dynamic random access memory (“DRAM”) arrays provides an effective second level of decoding resulting in a need for routing fewer column select lines to the sense amplifiers as compared with existing designs while concomitantly providing for shortened local data lines resulting in less undesired resistance and capacitance. The technique and architecture of the present invention requires no additional on-chip area to that required by existing designs and adds no new gate delays or pass gates to the critical read data or write data paths. This is effectuated by the incorporation of an address function with the read/write enable (“RWEN”) or separate read enable (“REN”) and write enable (“WEN”) signals. Consequently, half as many column select lines need be routed to the sense amplifiers since a second level of column decoding is provided.

Abstract: A data path decoding technique and architecture for integrated circuit memory devices and those devices incorporating embedded dynamic random access memory (“DRAM”) arrays provides an effective second level of decoding resulting in a need for routing fewer column select lines to the sense amplifiers as compared with existing designs while concomitantly providing for shortened local data lines resulting in less undesired resistance and capacitance. The technique and architecture of the present invention requires no additional on-chip area to that required by existing designs and adds no new gate delays or pass gates to the critical read data or write data paths. This is effectuated by the incorporation of an address function with the read/write enable (“RWEN”) or separate read enable (“REN”) and write enable (“WEN”) signals. Consequently, half as many column select lines need be routed to the sense amplifiers since a second level of column decoding is provided.

Abstract: An automatic delay technique for early “read” and “write” memory access operations in synchronous dynamic random access memory (“SDRAM”) devices and those integrated circuit devices employing embedded SDRAM arrays. A circuit and method is provided which controls the internal column select (“Yi”) and data signals such that the column address strobe (“/CAS”) signal is allowed to go “active” in advance of that otherwise possible in conjunction with conventional SDRAM arrays. In an exemplary embodiment, the column select signals (“read” or “write”) are delayed until either the corresponding, pre-decoded column address signal or the respective column clock signal is valid, whichever occurs later.

Abstract: A predecoder circuit for use in association with a memory circuit is shown to have a dynamic NAND gate formed by series-coupled transistors controlled by a bank active select signal and a row address selection signal. The predecoder circuit also includes a precharge circuit coupled to the dynamic NAND gate and controlled by a precharge signal. The predecoder circuit further includes a first inverter having an input terminal electrically coupled to the dynamic NAND gate and an output terminal selectively electrically connectable to at least one row decoder circuit for the memory circuit. The predecoder circuit finally includes a second inverter arranged in feedback with the first inverter to form a latch.

Abstract: A pre-charge and reference voltage technique operates on a DRAM memory array in which two additional rows of reference cells are added to the array. When the array starts the pre-charge cycle, the regular word line and latch P-channel bar signals both turn off and the complementary bit line pair is shorted together. These two lines charge share to create a half way voltage level (VCC/2) that is restored into the reference cell. After this voltage is restored into the reference cell, the bit lines are fully pre-charged to ground.

Abstract: A shared sense amplifier driver technique for integrated circuit devices including an array of memory cells comprises a plurality of sense amplifiers couplable to the memory cells with each of the sense amplifiers having an associated pull-up and pull-down switching device respectively coupled to a first and second latch node thereof. A first subset of the plurality of sense amplifiers have their first latch node (e.g. latch P-channel “LP”) electrically coupled and a second differing number subset of the plurality of sense amplifiers have their second latch node (e.g. latch N-channel “LN”) electrically coupled. By sharing the selected LP and LN nodes with more than one sense amplifier in a column, “write” recovery time can be significantly improved over that of conventional layouts and designs.

Abstract: A logic circuit has two internal voltage lines and includes additional upper and lower MOS transistors for coupling the external voltage supplies to the internal voltage nodes instead of using a single diode or transistor. These additional devices serve to clamp the internal voltages to a level that minimizes leakage current and maintains the data in the logic circuits.

Abstract: A time data compression technique which allows high speed integrated circuit (“IC”) memory devices to be tested at full speed with test equipment which is capable of operating at only at relatively slower speeds than that of the memory devices without increasing test time or decreasing production throughput. Through the use of the technique disclosed herein, data is initially sorted in time and them compared for a predetermined number of logic level “1s” or “0s” to be effectively compressed in time. This time compression allows high rate data streams to be tested at effectively slower rates. The technique of the present invention can be utilized to effectively reduce the data rate by one half, one quarter or to any sub-multiple of the normal memory frequency without increasing time in test.

Abstract: A system and method for low cost testing of integrated circuit devices at their rated speed during wafer probe testing while input signals to, and output signals from, the device may be operated at a lower speed. In the exemplary embodiment disclosed, a probe pad is used to enable a special test mode. When enabled, the on-chip clock generator enables a clock frequency doubler. The frequency doubler generates a 2X frequency clock from the 1X frequency external clock signals (two 1X clock phases with a 90 degree phase shift between the two clocks). The first phase of the clock uses the CLK input of the device and the second phase uses the device's CKE input.

Abstract: An integrated and constantly enabled on-chip test interface for use in verifying the functionality of high speed embedded memories such as synchronous dynamic random access memories (“SDRAM”) which allows for the utilization of existing, relatively low speed, (and hence low cost), testers to perform the testing. The interface allows for the verification of an embedded memory macro design utilizing a test interface which includes the memory macro and separate on-chip test circuitry so that half-rate, narrow word, input signals from a tester can perform all memory macro operations across the breadth of a wide memory macro input/output (“I/O”) architecture. The on-chip test circuitry may also include a synchronizing circuit to minimize skew between the external clock and the data output from the test chip.

Abstract: A delayed start oscillator includes an oscillator enable signal having first and second states thereof for selectively enabling and disabling the oscillator respectively. An oscillator output signal has first and second levels thereof responsive to the first state of the oscillator enable signal for providing an oscillator output signal. A timing circuit is coupled to a supply voltage line for providing a timing signal output indicative of a selected delayed start duration and a plurality of series connected inverting stages are coupled to receive the oscillator output signal and the timing signal. The oscillator output signal remains at a first level for the delayed start duration in response to the timing signal and subsequently transitions between the first and second levels at an operational frequency determined by the plurality of inverting stages until the oscillator enable signal transitions to the second state thereof.

Abstract: Wordline row redundancy scheme circuitry includes row shift circuitry and row decoder circuitry. If row shift redundancy is not desired, the row shift circuitry applies a first row shift control signal to the row shift control line. If row shift redundancy is desired, the row shift circuit applies a second row shift control signal to the row shift control line. The signal applied to the row shift control line actuates one of first and second electronic switches. Several electronic switches are series-coupled to the first and second electronic switches. The first electronic switch is also series-coupled to a first wordline select line. The second electronic switch is also series-coupled to a second wordline select line adjacent to the first wordline select line. Row address lines are coupled to the several electronic switches to carry row address selection control signals that selectively actuate its electronic switch.

Abstract: A self-timed data amplifier and method for an integrated circuit memory device which overcomes the power consumption problems of conventional static data amplifiers while providing a high speed amplification function within design margins. By self-timing the un-equilibration of the data lines ("DQ" and its complement "DQB"), powering the main data amplifier and latching its output all with the same clock that controls the column address for the device, a high speed, low power, low risk approach is achieved. In a particular embodiment of the present invention, this may be effectuated by the integration of an amplifying, latching and equilibration function wherein all of the related circuitry is controlled by the memory device Y-clock signal (YCLKB) and the write signal (WRITEB) signal. In operation, the YCLKB signal goes "low" when a column address is determined to be valid, which then allows the DQ and DQB lines to be driven.

Abstract: A circuit and method for concurrently addressing at least two rows of memory cells of a memory array of a memory device. By concurrently addressing at least two rows of memory cells during testing of the memory device during a burn-in period, the memory device can be tested in a reduced time period.

Abstract: Burst refresh mode circuitry is provided for a memory having cells in rows and columns, sense amplifiers and Latch N/Latch P driver circuitry, a RAS buffer, refresh counters, address buffers, row decoders, precharge circuitry producing shorting clocks, and a refresh detector circuit coupled to the Latch P circuitry to provide a restore finished (RF) signal indicative that a refresh cycle is substantially completed. Burst refresh mode entry circuitry detects proper conditions for entering burst refresh mode. An auto-refresh burst refresh mode circuit causes the RAS buffer to generate a new internal RAS signal. Burst refresh mode logic has counters to count the number of rows that have been refreshed. The system self-times the refreshing by responding to the restore finished signal. A delay circuit interposes a short delay for the precharge before another row is automatically refreshed in the burst refresh mode. Battery back-up mode circuitry is partially disabled.

Abstract: A memory device circuit that alters the input refresh addresses to access fewer memory cells to save power, or to address more memory cells to decrease the refresh time. The circuit contains a simple transistor configuration that blocks certain address bits, then substitutes active bits in their place to the address decoder. The circuit also includes a controller that is responsive to the memory device entering the refresh mode. When the device is used in refresh mode, the address bits may be passed unblocked to the address decoder for full user control.