Patents by Inventor Michael Chabinyc

Michael Chabinyc has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080092807
    Abstract: A transistor is formed by applying modifier coatings to source and drain contacts and/or to the channel region between those contacts. The modifier coatings are selected to adjust the surface energy pattern in the source/drain/channel region such that semiconductor printing fluid is not drawn away from the channel region. For example, the modifier coatings for the contacts can be selected to have substantially the same surface energy as the modifier coating for the channel region. Semiconductor printing fluid deposited on the channel region therefore settles in place (due to the lack of a surface energy differential) and forms a relatively thick active semiconductor region between the contacts. Alternatively, the modifier coatings can be selected to have lower surface energies than the modifier coating in the channel region, which actually causes semiconductor printing fluid to be drawn towards the channel region.
    Type: Application
    Filed: December 14, 2007
    Publication date: April 24, 2008
    Applicant: Palo Alto Research Center Incorporated
    Inventors: Michael Chabinyc, Ana Arias
  • Patent number: 7282129
    Abstract: An electrophoretic cell configuration and related method are disclosed that employ oppositely directed traveling electrical waves. The waves travel across the cell and samples undergoing separation. Various strategies are used to selectively direct the movement and arrangement of the samples and resulting sample patterns.
    Type: Grant
    Filed: June 12, 2003
    Date of Patent: October 16, 2007
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Meng H. Lean, Huangpin Ben Hsieh, John S. Fitch, Armin R. Völkel, Bryan Preas, Scott Elrod, Richard H. Bruce, Eric Peeters, Frank Torres, Michael Chabinyc
  • Publication number: 20070235410
    Abstract: Susceptibility of darkfield etch masks (majority of the mask area is opaque) to pinhole defects, transferred pattern, non-uniformity, etc. due to ejector dropout or drop misdirection, and long duty cycles due to large-area coverage, when using digital lithography (or print patterning) is addressed by using a clear-field print pattern that is then coated with etch resist material. The printed clear field pattern is selectively removed to form an inverse pattern (darkfield) within the coated resist layer. Etching then removes selected portions of an underlying (e.g., encapsulation, conductive, etc.) layer. Removal of the mask produces a layer with large-area features with substantially reduced defects.
    Type: Application
    Filed: March 31, 2006
    Publication date: October 11, 2007
    Inventors: William Wong, Scott Limb, Beverly Russo, Michael Chabinyc, Rene Lujan
  • Publication number: 20070221611
    Abstract: A process for fabricating fine features such as small gate electrodes on a transistor. The process involves the jet-printing of a mask and the plating of a metal to fabricate sub-pixel and standard pixel size features in one layer. Printing creates a small sub-pixel size gap mask for plating a fine feature. A second printed mask may be used to protect the newly formed gate and etch standard pixel size lines connecting the small gates.
    Type: Application
    Filed: March 24, 2006
    Publication date: September 27, 2007
    Inventors: Eugene Chow, William Wong, Michael Chabinyc, Ana Arias
  • Publication number: 20070221610
    Abstract: A method to pattern films into dimensions smaller than the printed pixel mask size. A printed mask is deposited on a thin film on a substrate. The second mask layer is selectively deposited onto the film, but not to the printed mask. A third mask is then printed onto the substrate to pattern a portion of the second mask. Certain solvents are then used to remove the printed mask but not the mask layer on the thin film. The mask layer is then used to form a pattern on the thin film in combination with etching. The features formed in the thin film are smaller than the smallest dimension of the printed mask. The coated mask layer can be a self-assembled mono-layer or other material that selectively binds to the thin film.
    Type: Application
    Filed: March 24, 2006
    Publication date: September 27, 2007
    Inventors: Eugene Chow, William Wong, Michael Chabinyc, Jeng Lu, Ana Arias
  • Publication number: 20070172774
    Abstract: A print patterned mask is formed a digital lithographic process on the surface of a photoresist or similar material layer. The print patterned mask is then used as a development or etching mask, and the underlying layer overdeveloped or overetched to undercut the print patterned mask. The mask may be removed and the underlying structure used an etch mask or as a final structure. Fine feature widths, narrower the minimum width of the print patterned mask features, may be obtained while realizing the benefits of digital lithography in the manufacturing process.
    Type: Application
    Filed: January 20, 2006
    Publication date: July 26, 2007
    Inventors: Scott Limb, William Wong, Steven Ready, Michael Chabinyc
  • Publication number: 20070172969
    Abstract: A digital lithographic process first deposits a mask layer comprised of print patterned mask features. The print patterned mask features define gaps into which a target material may be deposited, preferably through a digital lithographic process. The target material is cured or hardened, if necessary, into target features. The mask layer is then selectively removed. The remaining target features may then be used as exposure or etch masks, physical structures such as fluid containment elements, etc. Fine feature widths, narrower the minimum width of the print patterned mask features, may be obtained while realizing the benefits of digital lithography in the manufacturing process.
    Type: Application
    Filed: January 20, 2006
    Publication date: July 26, 2007
    Inventors: William Wong, Scott Limb, Michael Chabinyc, Beverly Russo, Rene Lujan
  • Publication number: 20070158644
    Abstract: A backplane circuit includes an array of organic thin-film transistors (OTFTs), each OTFT including a source contact, a drain contact, and an organic semiconductor region extending between the source and drain contacts. The drain contacts in each row are connected to an address line. The source and drain contacts and the address lines are fabricated using a multi-layer structure including a relatively thick base portion formed of a relatively inexpensive metal (e.g., aluminum or copper), and a relatively thin contact layer formed of a high work function, low oxidation metal (e.g., gold) that exhibits good electrical contact to the organic semiconductor, is formed opposite at least one external surface of the base, and is located at least partially in an interface region where the organic semiconductor contacts an underlying dielectric layer.
    Type: Application
    Filed: December 21, 2005
    Publication date: July 12, 2007
    Applicant: Palo Alto Research Center Incorporated
    Inventors: Michael Chabinyc, Rene Lujan, Ana Arias, Jackson Ho
  • Publication number: 20070023909
    Abstract: A method of forming a self-assembled interconnect structure is described. In the method, a contact pad surface and particles in a solution are brought together. The particles are selected such that they the particles adhere to the contact pad surface. Formation of a contact is completed by pressing an opposite contact into the particles such that an electrical connection is formed via the particles between the opposite contact pad and the substrate surface contact pad. The described self-assembled interconnect structure is particularly useful in display device fabrication.
    Type: Application
    Filed: July 27, 2005
    Publication date: February 1, 2007
    Inventors: David Fork, Thomas Hantschel, Michael Chabinyc
  • Publication number: 20070023908
    Abstract: A method of forming a self-assembled interconnect structure is described. In the method, a contact pad surface and particles in a solution are brought together. The particles are selected such that they the particles adhere to the contact pad surface. Formation of a contact is completed by pressing an opposite contact into the particles such that an electrical connection is formed via the particles between the opposite contact pad and the substrate surface contact pad. The described self-assembled interconnect structure is particularly useful in display device fabrication.
    Type: Application
    Filed: July 27, 2005
    Publication date: February 1, 2007
    Inventors: David Fork, Thomas Hantschel, Michael Chabinyc
  • Publication number: 20070023907
    Abstract: A method of forming a self-assembled interconnect structure is described. In the method, a contact pad surface and particles in a solution are brought together. The particles are selected such that they the particles adhere to the contact pad surface. Formation of a contact is completed by pressing an opposite contact into the particles such that an electrical connection is formed via the particles between the opposite contact pad and the substrate surface contact pad. The described self-assembled interconnect structure is particularly useful in display device fabrication.
    Type: Application
    Filed: July 27, 2005
    Publication date: February 1, 2007
    Inventors: David Fork, Thomas Hantschel, Michael Chabinyc
  • Patent number: 7156970
    Abstract: Various traveling wave grids and electrophoretic systems, and electrode assemblies using such grids, are disclosed. A configuration in which a voltage potential is used to load a biomolecule sample against a grid is disclosed. A unique strategy of using multiple, reconfigurable grids in such systems is also described. The strategy involves initially conducting a broad protein separation and then selectively tailoring one or more grids, and conducting one or more secondary processing operations. Related strategies and specific methods are additionally disclosed for separating samples of biomolecules and components thereof using the noted systems, assemblies, and grids.
    Type: Grant
    Filed: June 12, 2003
    Date of Patent: January 2, 2007
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Meng H. Lean, Huangpin Ben Hsieh, John S. Fitch, Armin R. Völkel, Bryan Preas, Scott Elrod, Richard H. Bruce, Eric Peeters, Frank Torres, Michael Chabinyc
  • Patent number: 7150813
    Abstract: Various gel electrophoretic assemblies and techniques are disclosed for providing unique isoelectric focusing (IEF) strategies. Several particular systems, assemblies and methods are provided that significantly reduce processing time, enable the use of reduced operating voltages, and produce analytical results with improved resolution.
    Type: Grant
    Filed: June 12, 2003
    Date of Patent: December 19, 2006
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Meng H. Lean, Huangpin Ben Hsieh, John S. Fitch, Armin R. Völkel, Bryan Preas, Scott Elrod, Richard H. Bruce, Eric Peeters, Frank Torres, Michael Chabinyc
  • Publication number: 20060159585
    Abstract: A detection system includes a detection device and an anti-evaporation device. The detection device comprises a region configured to merge at least two small drops and to detect a potential transient signal generated by the merger of the drops. The an anti-evaporation is configured to enclose the region and limit evaporation from the region. A method for detecting a signal includes the following steps: depositing drops of potentially reactive chemical solutions on a detection device within a drop-merging region; placing an anti-evaporation device over the drop-merging region to form a seal around the drop-merging region; merging the drops of potentially reactive chemical solutions; and measuring a signal occurring within the merged solution drops.
    Type: Application
    Filed: January 18, 2005
    Publication date: July 20, 2006
    Inventors: Francisco Torres, Michael Chabinyc, Scott Elrod, Eric Peeters, Gregory Anderson, Alan Bell, Richard Bruce
  • Publication number: 20060131124
    Abstract: A Vertical Cavity Surface Emitting Laser (VCSEL) assembly including a VCSEL structure having a light-emitting region located on its surface, a relatively wettable region of a surface modifier coating formed over the light emitting region, and a microlens formed on the relatively wettable region. A relatively non-wettable region of the surface modifier coating is formed around the light-emitting region (e.g., on the electrode surrounding the light-emitting region). The surface modifier coating is formed, for example, from one or more organothiols that change the surface energies of the light-emitting region and/or the electrode to facilitate self-assembly and self-registration of the microlens material. The microlens material is printed, microjetted, or dip coated onto the VCSEL structure such that the microlens material wets to the relatively wettable region, thereby forming a liquid bead that is reliably positioned over the light-emitting region. The liquid bead is then cured to form the microlens.
    Type: Application
    Filed: December 17, 2004
    Publication date: June 22, 2006
    Applicant: Palo Alto Research Center Incorporated
    Inventors: Michael Chabinyc, Patrick Maeda, Christopher Chua
  • Publication number: 20060131266
    Abstract: Two different processing techniques are utilized to respectively form high resolution features and low resolution features in a critical layer of an electronic device, and in particular a large area electronic device. High resolution features are formed by soft lithography, and low resolution features are formed by jet-printing or using a jet-printed etch mask. Jet-printing is also used to stitch misaligned structures. Alignment marks are generated with the features to coordinate the various processing steps and to automatically control the stitching process. Thin-film transistors are formed by generating gate structures using a first jet-printed etch mask, forming source/drain electrodes using soft lithography, forming interconnect structures using a second jet-printed etch mask, and then depositing semiconductor material over the source/drain electrodes.
    Type: Application
    Filed: December 20, 2004
    Publication date: June 22, 2006
    Applicant: Palo Alto Research Center Incorporated
    Inventors: Robert Street, William Wong, Alberto Salleo, Michael Chabinyc
  • Publication number: 20060115945
    Abstract: A transistor is formed by applying modifier coatings to source and drain contacts and/or to the channel region between those contacts. The modifier coatings are selected to adjust the surface energy pattern in the source/drain/channel region such that semiconductor printing fluid is not drawn away from the channel region. For example, the modifier coatings for the contacts can be selected to have substantially the same surface energy as the modifier coating for the channel region. Semiconductor printing fluid deposited on the channel region therefore settles in place (due to the lack of a surface energy differential) and forms a relatively thick active semiconductor region between the contacts. Alternatively, the modifier coatings can be selected to have lower surface energies than the modifier coating in the channel region, which actually causes semiconductor printing fluid to be drawn towards the channel region.
    Type: Application
    Filed: January 12, 2006
    Publication date: June 1, 2006
    Applicant: Palo Alto Research Center Incorporated
    Inventors: Michael Chabinyc, Ana Arias
  • Publication number: 20060063369
    Abstract: Controlled overetching is utilized to produce metal patterns having gaps that are smaller than the resolution limits of the feature patterning (e.g., photolithography) process utilized to produce the metal patterns. A first metal layer is formed and masked, and exposed regions are etched away. The etching process is allowed to continue in a controlled manner to produced a desired amount of over-etching (i.e., undercutting the mask) such that an edge of the first metal layer is offset from an edge of the mask by a predetermined gap distance. A second metal layer is then deposited such that an edge of the second metal layer is spaced from the first metal layer by the predetermined gap distance. The metal gap is used to define, for example, transistor channel lengths, thereby facilitating the production of transistors having channel lengths defined by etching process control that are smaller than the process resolution limits.
    Type: Application
    Filed: September 17, 2004
    Publication date: March 23, 2006
    Applicant: Palo Alto Research Center Incorporated
    Inventors: JengPing Lu, Jackson Ho, Chinwen Shih, Michael Chabinyc, William Wong
  • Publication number: 20060057851
    Abstract: A method and system for masking a surface to be etched is described. The method includes the operation of heating a phase-change masking material and using a droplet source to eject droplets of a masking material for deposit on a thin-film or other substrate surface to be etched. The temperature of the thin-film or substrate surface is controlled such that the droplets rapidly freeze after upon contact with the thin-film or substrate surface. The thin-film or substrate is then treated to alter the surface characteristics, typically by depositing a self assembled monolayer on the surface. After deposition, the masking material is removed. A material of interest is then deposited over the substrate such that the material adheres only to regions not originally covered by the mask such that the mask acts as a negative resist. Using such techniques, feature sizes of devices smaller than the smallest droplet printed may be fabricated.
    Type: Application
    Filed: October 14, 2005
    Publication date: March 16, 2006
    Inventors: William Wong, Steven Ready, Stephen White, Alberto Salleo, Michael Chabinyc
  • Publication number: 20050269570
    Abstract: A transistor is formed by applying modifier coatings to source and drain contacts and/or to the channel region between those contacts. The modifier coatings are selected to adjust the surface energy pattern in the source/drain/channel region such that semiconductor printing fluid is not drawn away from the channel region. For example, the modifier coatings for the contacts can be selected to have substantially the same surface energy as the modifier coating for the channel region. Semiconductor printing fluid deposited on the channel region therefore settles in place (due to the lack of a surface energy differential) and forms a relatively thick active semiconductor region between the contacts. Alternatively, the modifier coatings can be selected to have lower surface energies than the modifier coating in the channel region, which actually causes semiconductor printing fluid to be drawn towards the channel region.
    Type: Application
    Filed: June 8, 2004
    Publication date: December 8, 2005
    Applicant: Palo Alto Research Center Incorporated
    Inventors: Michael Chabinyc, Ana Arias