Patents by Inventor Michael D. Rostoker

Michael D. Rostoker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6978319
    Abstract: A protocol translation cable assembly includes a first connector having a first plurality of pins, a second connector having a second plurality of pins, and an electrical cable coupling the first connector to the second connector, where the electrical cable includes a plurality of conductors. The protocol translation cable assembly further includes translation circuitry coupled to at least some of the plurality of wires of the electric cable at points between the first plurality of pins of the first connector and the second plurality of pins of the second connector. The translation circuitry preferably derives its power from the electrical cable such that separate power supplies are not required. The cable assembly therefore provides transparent “plug-and-play” capabilities.
    Type: Grant
    Filed: August 18, 2000
    Date of Patent: December 20, 2005
    Assignee: Kawasaki Microelectronics Inc.
    Inventors: Michael D. Rostoker, Joel Silverman
  • Patent number: 6810434
    Abstract: An integrated circuit architecture for multimedia processing. A single integrated circuit (IC) operates as a system or subsystem, and is adaptable to processing a variety of multimedia algorithms, whether proprietary or open. Hard macros, either analog or digital, can be incorporated. The IC can also contain audio/video CODECs to suit different standards, as well as other peripheral devices which may be required for multimedia applications. An electronic component (e.g., integrated circuit) incorporating the technique is suitably included in a system or subsystem having electrical functionality, such as general purpose computers, telecommunications devices, and the like.
    Type: Grant
    Filed: August 14, 2001
    Date of Patent: October 26, 2004
    Assignee: Kawasaki Microelectronics, Inc.
    Inventors: Kumaraguru Muthujumaraswathy, Michael D. Rostoker
  • Patent number: 6754196
    Abstract: A plurality of devices communicate information over a wireless network at radio frequencies. The information includes digital audio, video and data. Bandwidth among the devices is dynamically allocated, the allocation being based upon the needs of the devices. One embodiment of the wireless network is a Time Division Multiple Access network. Another embodiment is a wireless Ethernet. Yet another embodiment is a Frequency Division Multiplexed network.
    Type: Grant
    Filed: April 20, 1998
    Date of Patent: June 22, 2004
    Assignee: LSI Logic Corporation
    Inventors: John Daane, Michael D. Rostoker, Sandeep Jaggi
  • Patent number: 6493658
    Abstract: A physical design automation system produces an optimal placement of microelectronic components or cells on an integrate circuit chip. An initial population of possible cell placements is generated, and repeatedly altered using simulated on or other fitness improvement algorithm to progressively increase the fitnesses (decrease the costs) of the placements. After each alteration step, the fitnesses of the placements are calculated, and less fit placements are discarded in favor of more fit placements. After a termination criterion is reached, the placement having the highest fitness is designated as the optimal placement. Two or more fitness improvement algorithms are available, and are optimally switched from one to the other in accordance with an optimization criterion to maximize convergence of the placements toward the optimal configuration.
    Type: Grant
    Filed: April 19, 1994
    Date of Patent: December 10, 2002
    Assignee: LSI Logic Corporation
    Inventors: James S. Koford, Michael D. Rostoker, Edwin R. Jones, Douglas B. Boyle, Ranko Scepanovic
  • Patent number: 6484065
    Abstract: An efficient DSP or MPU is combined with efficient DRAM on a single IC die. To optimize the embedded memory, the chip includes wide-band connections to DRAM. Row and column addresses of DRAM can be applied at the same time using wide address busses. Additional metal lines lower the resistance of the word line in the DRAM circuits. For certain process steps, the processor block is masked off and the process steps unique to the fabrication of memory are performed on the memory block, and vice-versa. Process steps which are common to the processor and memory blocks can be performed simultaneously on the processor and memory blocks without masking off either block. Certain process steps can be employed in the fabrication of the one of the two processor and memory blocks in addition to or in lieu of processes normally used in the fabrication of that block. An electronic component (e.g.
    Type: Grant
    Filed: October 5, 1998
    Date of Patent: November 19, 2002
    Assignee: Kawasaki Microelectronics, Inc.
    Inventors: Peter K. Yu, Michael D. Rostoker
  • Patent number: 6470482
    Abstract: A system for interactive design, synthesis and simulation of an electronic system allowing a user to design a system either by specification of a behavioral model in a high level language such as VHDL or by graphical entry. The user can view full or partial simulation and design results simultaneously, on a single display window. The synthesis process uses a systematic technique to map and enforce consistency of the semantics imbedded in the intent of the original, high-level descriptions. The design activity is generally a series of transformations operating upon various levels of design representations. At each level, the design can be simulated and reviewed in schematic diagram form. The simulation results can be displayed immediately adjacent to signal lines on the diagram to which they correspond. In one embodiment, design rule violations are processed by an expert system to suggest possible corrections or alterations to the design which will eliminate the design rule violations.
    Type: Grant
    Filed: August 5, 1996
    Date of Patent: October 22, 2002
    Assignee: LSI Logic Corporation
    Inventors: Michael D. Rostoker, Carlos Dangelo, Daniel R. Watkins
  • Patent number: 6418353
    Abstract: Automated photolithography of integrated circuit wafers is enabled with a processor connected to a Rayleigh derator, a form factor generator, a logic synthesizer, a layout generator, a lithography module and a wafer process. The Rayleigh derator receives manufacturing information resulting from yield data in the wafer process, and this manufacturing data is then used to derate the theoretical minimum feature size available for etching wafer masks given a known light source and object lens numerical aperture. This minimum feature size is then used by a form factor generator in sizing transistors in a net list to their smallest manufacturable size. A logic synthesizer then converts the net list into a physical design using a layout generator combined with user defined constraints. This physical design is then used by the mask lithography module to generate wafer masks for use in the semiconductor manufacturing. Manufacturing data including process and.
    Type: Grant
    Filed: April 22, 1998
    Date of Patent: July 9, 2002
    Assignee: LSI Logic Corporation
    Inventors: Michael D. Rostoker, Nicholas F. Pasch, Ashok K. Kapoor
  • Patent number: 6407434
    Abstract: Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60°. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed.
    Type: Grant
    Filed: August 21, 1995
    Date of Patent: June 18, 2002
    Assignee: LSI Logic Corporation
    Inventors: Michael D. Rostoker, James S. Koford, Ranko Scepanovic, Edwin R. Jones, Gobi R. Padmanahben, Ashok K. Kapoor, Valeriy B. Kudryavtsev, Alexander E. Andreev, Stanislav V. Aleshin, Alexander S. Podkolzin
  • Patent number: 6373447
    Abstract: One or more antennas are formed on an integrated circuit (IC) chip and connected to other circuitry on the IC chip. Antenna configurations include loop, multi-turn loop, square spiral, long wire, or dipole. The antenna may be formed to have two or more segments which can selectively be connected to one another to alter an effective length of the antenna. Two antennas may be formed in two different metallization layers separated by an insulating layer. Additionally, an antenna may be incorporated in a heat sink structure that is joined to the IC chip. IC chips having antennas are suitably included in a system or subsystem having electrical functionality, such as general purpose computers, telecommunications devices, and the like.
    Type: Grant
    Filed: December 28, 1998
    Date of Patent: April 16, 2002
    Assignee: Kawasaki Steel Corporation
    Inventors: Michael D. Rostoker, Kumaraguru Muthukumaraswamy
  • Patent number: 6370603
    Abstract: An interface device is provided which enables communications between devices having disparate protocols (e.g., USB and Ethernet), and can be fabricated on a single integrated circuit (IC) chip. A system incorporating the interface device provides plug-and-play capability for both MAC and nonMAC environments. A “smart” cable incorporating the interface device has the ability to recognize what type of external device using what type of protocol is connected to the “other” end of the cable, thereby enabling a host to communicate with the external device. An electronic component (e.g., integrated circuit) incorporating the technique is suitably included in a system or subsystem having electrical functionality, such as general purpose computers, telecommunications devices, and the like.
    Type: Grant
    Filed: October 5, 1998
    Date of Patent: April 9, 2002
    Assignee: Kawasaki Microelectronics, Inc.
    Inventors: Joel Silverman, Michael D. Rostoker
  • Publication number: 20020026539
    Abstract: An integrated circuit architecture for multimedia processing. A single integrated circuit (IC) operates as a system or subsystem, and is adaptable to processing a variety of multimedia algorithms, whether proprietary or open. Hard macros, either analog or digital, can be incorporated. The IC can also contain audio/video CODECs to suit different standards, as well as other peripheral devices which may be required for multimedia applications. An electronic component (e.g., integrated circuit) incorporating the technique is suitably included in a system or subsystem having electrical functionality, such as general purpose computers, telecommunications devices, and the like.
    Type: Application
    Filed: August 14, 2001
    Publication date: February 28, 2002
    Inventors: Kumaraguru Muthukumaraswamy, Michael D. Rostoker
  • Patent number: 6312980
    Abstract: Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60°. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed.
    Type: Grant
    Filed: June 5, 1998
    Date of Patent: November 6, 2001
    Assignee: LSI Logic Corporation
    Inventors: Michael D. Rostoker, James S. Koford, Ranko Scepanovic, Edwin R. Jones, Gobi R. Padmanahben, Ashok K. Kapoor, Valeriv B. Kudryavtsev, Alexander E. Andreev, Stanislav V. Aleshin, Alexander S. Podkolzin
  • Patent number: 6279045
    Abstract: An integrated circuit architecture for multimedia processing. A single integrated circuit (IC) operates as a system or subsystem, and is adaptable to processing a variety of multimedia algorithms, whether proprietary or open. Hard macros, either analog or digital, can be incorporated. The IC can also contain audio/video CODECs to suit different standards, as well as other peripheral devices which may be required for multimedia applications. An electronic component (e.g., integrated circuit) incorporating the technique is suitably included in a system or subsystem having electrical functionality, such as general purpose computers, telecommunications devices, and the like.
    Type: Grant
    Filed: October 5, 1998
    Date of Patent: August 21, 2001
    Assignee: Kawasaki Steel Corporation
    Inventors: Kumaraguru Muthujumaraswathy, Michael D. Rostoker
  • Patent number: 6279133
    Abstract: Method and apparatus for significantly improving the reliability of multilevel (MLT) memory architecture. Before writing to MLT architecture, each MLT word is encoded into a coded bit stream in such a way that the resultant coded data contains the original word plus additional digits which are a function of the content of memory. During the reading of the memory, the stored data is decoded, and takes advantage of redundancy to correct and eliminate errors introduced during read and write operations of the MLT architecture. The invention is useful for systems such as general-purpose computers (PCs, workstations, etc.), telecommunications devices (telephones—wired and wireless, switches, hubs, routers, etc.), audio and visual devices (recording and playback, editing, format switching, compression, etc.), vehicles (automobiles, aircraft, trains, boats, satellites, spacecraft, etc.). Systems and subsystems may be incorporated on a single integrated circuit (IC) die having MLT RAM or enhanced MLT memory.
    Type: Grant
    Filed: October 5, 1998
    Date of Patent: August 21, 2001
    Assignee: Kawasaki Steel Corporation
    Inventors: Manouchehr Vafai, Michael D. Rostoker
  • Patent number: 6229227
    Abstract: Programmability for on-chip passive components such as resistors, capacitors and inductors is achieved by forming a first passive component such as a resistor, capacitor or inductor, and at least one additional passive component (again, such as resistor, capacitor or inductor), and at least one means for selectively switching selected ones of the at least two additional passive components in series or in parallel with the first passive component are provided on an integrated circuit (IC) chip. The series/parallel connected first passive component and additional passive components are connected between two terminals of the IC chip whereat it is desired to establish a passive component value (e.g., resistance, capacitance or inductance). In this manner, one of a plurality of possible total (overall) values may be established.
    Type: Grant
    Filed: December 28, 1998
    Date of Patent: May 8, 2001
    Assignee: Kawasaki Steel Corporation
    Inventors: Kumaraguru Muthukumaraswamy, Michael D. Rostoker
  • Patent number: 6181011
    Abstract: An integrated circuit (IC chip) has features such as conductive lines. The features have a thickness “T”, a width “W”, and a distance (spacing) “S” between adjacent features, and one or more of the following aspect ratio relationships: a ratio of width:thickness (W/T) is less than or equal to 0.7:1; a ratio of width:spacing (W:S) is less than or equal to 0.7:1; and a ratio of thickness:spacing (T:S) is less than or equal to 0.1:1. These relationships are particularly applicable to ICs having a feature geometry (width) of less than 0.16 microns and operating at less than 1.8 volts. An IC incorporating such features is suitably included in a system or subsystem having electrical functionality, such as general purpose computers, telecommunications devices, and the like.
    Type: Grant
    Filed: December 29, 1998
    Date of Patent: January 30, 2001
    Assignee: Kawasaki Steel Corporation
    Inventors: Michael D. Rostoker, Kumaraguru Muthukumaraswamy
  • Patent number: 6155725
    Abstract: A large number of possible cell placements for an integrated circuit chip are evaluated to determine which has the highest fitness in accordance with a predetermined criteria such as interconnect congestion. Each cell placement, which constitutes an individual permutation of cells from a population of possible permutations, is represented as an initial cell placement in combination with a list of individual cell transpositions or swaps by which the cell placement can be derived from the initial cell placement. A cell placement can be genetically mutated and/or inverted by adding swaps to the list for its cell placement which designates cells to be transposed. Genetic crossover can be performed by transposing swaps between the lists for two cell placements. This cell representation and transposition method enables any type of cell transposition to be performed without loss or duplication of cells or generation of illegal placements.
    Type: Grant
    Filed: April 19, 1994
    Date of Patent: December 5, 2000
    Assignee: LSI Logic Corporation
    Inventors: Ranko Scepanovic, James S Koford, Edwin R. Jones, Douglas B. Boyle, Michael D. Rostoker
  • Patent number: 6147890
    Abstract: Content Addressable Memory (CAM) core is integrated and interfaced with a configurable logic core (e.g., FPGA) on a single integrated circuit (IC) chip to permit a user to change algorithms for and to tailor word length to a particular application. Significant improvements in fetch times and overhead are achieved. An electronic component (e.g., integrated circuit) incorporating the technique is suitably included in a system or subsystem having electrical functionality, such as general purpose computers, telecommunications devices, and the like.
    Type: Grant
    Filed: October 5, 1998
    Date of Patent: November 14, 2000
    Assignee: Kawasaki Steel Corporation
    Inventors: Keiichi Kawana, Michael D. Rostoker
  • Patent number: 6131125
    Abstract: A protocol translation cable assembly includes a first connector having a first plurality of pins, a second connector having a second plurality of pins, and an electrical cable coupling the first connector to the second connector, where the electrical cable includes a plurality of conductors. The protocol translation cable assembly further includes translation circuitry coupled to at least some of the plurality of wires of the electric cable at points between the first plurality of pins of the first connector and the second plurality of pins of the second connector. The translation circuitry preferably derives its power from the electrical cable such that separate power supplies are not required. The cable assembly therefore provides transparent "plug-and-play" capabilities.
    Type: Grant
    Filed: November 14, 1997
    Date of Patent: October 10, 2000
    Assignee: Kawasaki LSI U.S.A., Inc.
    Inventors: Michael D. Rostoker, Joel Silverman
  • Patent number: RE38900
    Abstract: Automated photolithography of integrated circuit wafers is enabled with a processor connected to a Rayleigh derator, a form factor generator, a logic synthesizer, a layout generator, a lithography module and a wafer process. The Rayleigh derator receives manufacturing information resulting from yield data in the wafer process, and this manufacturing data is then used to derate the theoretical minimum feature size available for etching wafer masks given a known light source and object lens numerical aperture. This minimum feature size is then used by a form factor generator in sizing transistors in a net list to their smallest manufacturable size. A logic synthesizer then converts the net list into a physical design using a layout generator combined with user defined constraints. This physical design is then used by the mask lithography module to generate wafer masks for use in the semiconductor manufacturing.
    Type: Grant
    Filed: March 19, 1999
    Date of Patent: November 29, 2005
    Assignee: LSI Logic Corporation
    Inventors: Michael D. Rostoker, Nicholas F. Pasch, Ashok K. Kapoor