Abstract: A memory structure is provided that avoids high resistance due to the galvanic effect. The high resistance is reduced and/or eliminated by providing a T-shaped bottom electrode structure of uniform construction (i.e., a single piece). The T-shaped bottom electrode structure includes a narrow base portion and a wider shelf portion. The shelf portion of the T-shaped bottom electrode structure has a planar topmost surface in which a MTJ pillar forms an interface with.

Abstract: A memory structure is provided that avoids high resistance due to the galvanic effect. The high resistance is reduced and/or eliminated by providing a T-shaped bottom electrode structure of uniform construction (i.e., a single piece). The T-shaped bottom electrode structure includes a narrow base portion and a wider shelf portion. The shelf portion of the T-shaped bottom electrode structure has a planar topmost surface in which a MTJ pillar forms an interface with.

Abstract: The present disclosure relates to integrated circuits and to methods of manufacturing interconnects of integrated circuits. For example, an integrated circuit includes a surface of the integrated circuit and an interconnect formed on the surface and comprising a metal. An average grain size of the metal of the interconnect is greater than or equal to at least half of a line width of the interconnect. In another example, a method for manufacturing an interconnect of an integrated circuit includes depositing a layer of a metal onto a surface of the integrated circuit, annealing the metal, patterning a first hard mask for placement over the metal and forming a line of the interconnect and a first via of the interconnect by performing a timed etch of the metal using the first hard mask.

Abstract: A method is presented for establishing a top contact to a magnetic tunnel junction (MTJ) device, the method including selectively etching, via a first etching process, an oxide layer to expose a top surface of a nitride layer of a dummy fill shape and selectively etching, via a second etching process, a top portion of the nitride layer of the dummy fill shape to expose a top surface thereof. The method further includes selectively etching, via the second etching process, the oxide layer to expose a top surface of a nitride layer of the MTJ device, and selectively etching, via the first etching process, a top portion of the nitride layer of the MTJ device to expose a top surface thereof such that a height of the MTJ device is approximately equal to a height of the dummy fill shape.

Abstract: A technique relates to manufacturing a nanogap. An oxide layer is disposed on top of a substrate. A release layer is disposed in a pattern on top of the oxide layer. A patterned trench is etched into the oxide layer using the pattern of the release layer. A metal layer is disposed on the release layer and in the patterned trench. A polish removes the release layer, thereby removing both the release layer and a portion of the metal layer having been disposed on top of the release layer, such that the metal layer remaining includes a first metal part and a second metal part connected by a metal nanowire. The metal layer remaining is coplanar with the oxide layer. A nanochannel is formed in the oxide layer in a region of the metal nanowire. The nanogap is formed in the metal nanowire separating the first and second metal parts.

Abstract: The present disclosure relates to integrated circuits and to methods of manufacturing interconnects of integrated circuits. For example, an integrated circuit includes a surface of the integrated circuit and an interconnect formed on the surface and comprising a metal. An average grain size of the metal of the interconnect is greater than or equal to at least half of a line width of the interconnect. In another example, a method for manufacturing an interconnect of an integrated circuit includes depositing a layer of a metal onto a surface of the integrated circuit, annealing the metal, patterning a first hard mask for placement over the metal and forming a line of the interconnect and a first via of the interconnect by performing a timed etch of the metal using the first hard mask.

Abstract: A method is presented for establishing a top contact to a magnetic tunnel junction (MTJ) device, the method including selectively etching, via a first etching process, an oxide layer to expose a top surface of a nitride layer of a dummy fill shape and selectively etching, via a second etching process, a top portion of the nitride layer of the dummy fill shape to expose a top surface thereof. The method further includes selectively etching, via the second etching process, the oxide layer to expose a top surface of a nitride layer of the MTJ device, and selectively etching, via the first etching process, a top portion of the nitride layer of the MTJ device to expose a top surface thereof such that a height of the MTJ device is approximately equal to a height of the dummy fill shape.

Abstract: The present disclosure relates to integrated circuits and to methods of manufacturing interconnects of integrated circuits. For example, an integrated circuit includes a surface of the integrated circuit and an interconnect formed on the surface and comprising a metal. An average grain size of the metal of the interconnect is greater than or equal to at least half of a line width of the interconnect. In another example, a method for manufacturing an interconnect of an integrated circuit includes depositing a layer of a metal onto a surface of the integrated circuit, annealing the metal, patterning a first hard mask for placement over the metal and forming a line of the interconnect and a first via of the interconnect by performing a timed etch of the metal using the first hard mask.

Abstract: A method is presented for establishing a top contact to a magnetic tunnel junction (MTJ) device, the method including selectively etching, via a first etching process, an oxide layer to expose a top surface of a nitride layer of a dummy fill shape and selectively etching, via a second etching process, a top portion of the nitride layer of the dummy fill shape to expose a top surface thereof. The method further includes selectively etching, via the second etching process, the oxide layer to expose a top surface of a nitride layer of the MTJ device, and selectively etching, via the first etching process, a top portion of the nitride layer of the MTJ device to expose a top surface thereof such that a height of the MTJ device is approximately equal to a height of the dummy fill shape.

Abstract: A method is presented for establishing a top contact to a magnetic tunnel junction (MTJ) device, the method including selectively etching, via a first etching process, an oxide layer to expose a top surface of a nitride layer of a dummy fill shape and selectively etching, via a second etching process, a top portion of the nitride layer of the dummy fill shape to expose a top surface thereof. The method further includes selectively etching, via the second etching process, the oxide layer to expose a top surface of a nitride layer of the MTJ device, and selectively etching, via the first etching process, a top portion of the nitride layer of the MTJ device to expose a top surface thereof such that a height of the MTJ device is approximately equal to a height of the dummy fill shape.

Abstract: A method is presented for establishing a top contact to a magnetic tunnel junction (MTJ) device, the method including selectively etching, via a first etching process, an oxide layer to expose a top surface of a nitride layer of a dummy fill shape and selectively etching, via a second etching process, a top portion of the nitride layer of the dummy fill shape to expose a top surface thereof. The method further includes selectively etching, via the second etching process, the oxide layer to expose a top surface of a nitride layer of the MTJ device, and selectively etching, via the first etching process, a top portion of the nitride layer of the MTJ device to expose a top surface thereof such that a height of the MTJ device is approximately equal to a height of the dummy fill shape.

Abstract: A technique relates to a nanogap array. A substrate has been anisotropically etched with trenches that have tapered sidewalls. A sacrificial layer is on bottoms and the tapered sidewalls of the trenches. A filling material is formed on top of the sacrificial layer in the trenches. Nanogaps are formed where at least a portion of the sacrificial layer has been removed from the tapered sidewalls of the trenches while the sacrificial layer remains on the bottoms of the trenches. Each of the nanogaps is formed between one tapered sidewall of the substrate and a corresponding tapered sidewall of the filling material. The one tapered sidewall of the substrate opposes the corresponding tapered sidewall. A capping layer is disposed on top of the substrate and the filling material, such that the nanogaps are covered but not filled in.

Abstract: A technique relates to manufacturing a nanogap. An oxide layer is disposed on top of a substrate. A release layer is disposed in a pattern on top of the oxide layer. A patterned trench is etched into the oxide layer using the pattern of the release layer. A metal layer is disposed on the release layer and in the patterned trench. A polish removes the release layer, thereby removing both the release layer and a portion of the metal layer having been disposed on top of the release layer, such that the metal layer remaining includes a first metal part and a second metal part connected by a metal nanowire. The metal layer remaining is coplanar with the oxide layer. A nanochannel is formed in the oxide layer in a region of the metal nanowire. The nanogap is formed in the metal nanowire separating the first and second metal parts.

Abstract: A technique relates to a nanogap array. A substrate has been anisotropically etched with trenches that have tapered sidewalls. A sacrificial layer is on bottoms and the tapered sidewalls of the trenches. A filling material is formed on top of the sacrificial layer in the trenches. Nanogaps are formed where at least a portion of the sacrificial layer has been removed from the tapered sidewalls of the trenches while the sacrificial layer remains on the bottoms of the trenches. Each of the nanogaps is formed between one tapered sidewall of the substrate and a corresponding tapered sidewall of the filling material. The one tapered sidewall of the substrate opposes the corresponding tapered sidewall. A capping layer is disposed on top of the substrate and the filling material, such that the nanogaps are covered but not filled in.

Abstract: A technique relates to manufacturing a nanogap. An oxide layer is disposed on top of a substrate. A release layer is disposed in a pattern on top of the oxide layer. A patterned trench is etched into the oxide layer using the pattern of the release layer. A metal layer is disposed on the release layer and in the patterned trench. A polish removes the release layer, thereby removing both the release layer and a portion of the metal layer having been disposed on top of the release layer, such that the metal layer remaining includes a first metal part and a second metal part connected by a metal nanowire. The metal layer remaining is coplanar with the oxide layer. A nanochannel is formed in the oxide layer in a region of the metal nanowire. The nanogap is formed in the metal nanowire separating the first and second metal parts.

Abstract: A technique relates to manufacturing a nanogap. An oxide layer is disposed on top of a substrate. A release layer is disposed in a pattern on top of the oxide layer. A patterned trench is etched into the oxide layer using the pattern of the release layer. A metal layer is disposed on the release layer and in the patterned trench. A polish removes the release layer, thereby removing both the release layer and a portion of the metal layer having been disposed on top of the release layer, such that the metal layer remaining includes a first metal part and a second metal part connected by a metal nanowire. The metal layer remaining is coplanar with the oxide layer. A nanochannel is formed in the oxide layer in a region of the metal nanowire. The nanogap is formed in the metal nanowire separating the first and second metal parts.

Abstract: A technique relates to a nanogap array. A substrate has been anisotropically etched with trenches that have tapered sidewalls. A sacrificial layer is on bottoms and the tapered sidewalls of the trenches. A filling material is formed on top of the sacrificial layer in the trenches. Nanogaps are formed where at least a portion of the sacrificial layer has been removed from the tapered sidewalls of the trenches while the sacrificial layer remains on the bottoms of the trenches. Each of the nanogaps is formed between one tapered sidewall of the substrate and a corresponding tapered sidewall of the filling material. The one tapered sidewall of the substrate opposes the corresponding tapered sidewall. A capping layer is disposed on top of the substrate and the filling material, such that the nanogaps are covered but not filled in.

Abstract: A technique relates to a nanogap array. A substrate has been anisotropically etched with trenches that have tapered sidewalls. A sacrificial layer is on bottoms and the tapered sidewalls of the trenches. A filling material is formed on top of the sacrificial layer in the trenches. Nanogaps are formed where at least a portion of the sacrificial layer has been removed from the tapered sidewalls of the trenches while the sacrificial layer remains on the bottoms of the trenches. Each of the nanogaps is formed between one tapered sidewall of the substrate and a corresponding tapered sidewall of the filling material. The one tapered sidewall of the substrate opposes the corresponding tapered sidewall. A capping layer is disposed on top of the substrate and the filling material, such that the nanogaps are covered but not filled in.

Abstract: The present disclosure relates to integrated circuits and to methods of manufacturing interconnects of integrated circuits. For example, an integrated circuit includes a surface of the integrated circuit and an interconnect formed on the surface and comprising a metal. An average grain size of the metal of the interconnect is greater than or equal to at least half of a line width of the interconnect. In another example, a method for manufacturing an interconnect of an integrated circuit includes depositing a layer of a metal onto a surface of the integrated circuit, annealing the metal, patterning a first hard mask for placement over the metal and forming a line of the interconnect and a first via of the interconnect by performing a timed etch of the metal using the first hard mask.

Abstract: A nanogap of controlled width in-between noble metals is produced using sidewall techniques and chemical-mechanical-polishing. Electrical connections are provided to enable current measurements across the nanogap for analytical purposes. The nanogap in-between noble metals may also be formed inside a Damascene trench. The nanogap in-between noble metals may also be inserted into a crossed slit nanopore framework. A noble metal layer on the side of the nanogap may have sub-layers serving the purpose of multiple simultaneous electrical measurements.