Patents by Inventor Michael G. Lavelle
Michael G. Lavelle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10019777Abstract: A high-speed ring topology. In one embodiment, two base chip types are required: a “drawing” chip, LoopDraw, and an “interface” chip, LoopInterface. Each of these chips have a set of pins that supports an identical high speed point to point unidirectional input and output ring interconnect interface: the LoopLink. The LoopDraw chip uses additional pins to connect to several standard memories that form a high bandwidth local memory sub-system. The LoopInterface chip uses additional pins to support a high speed host computer host interface, at least one video output interface, and possibly also additional non-local interconnects to other LoopInterface chip(s).Type: GrantFiled: October 21, 2016Date of Patent: July 10, 2018Assignee: GULA CONSULTING LIMITED LIABILITY COMPANYInventors: Michael F. Deering, Michael G. Lavelle
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Publication number: 20170103494Abstract: A high-speed ring topology. In one embodiment, two base chip types are required: a “drawing” chip, LoopDraw, and an “interface” chip, LoopInterface. Each of these chips have a set of pins that supports an identical high speed point to point unidirectional input and output ring interconnect interface: the LoopLink. The LoopDraw chip uses additional pins to connect to several standard memories that form a high bandwidth local memory sub-system. The LoopInterface chip uses additional pins to support a high speed host computer host interface, at least one video output interface, and possibly also additional non-local interconnects to other LoopInterface chip(s).Type: ApplicationFiled: October 21, 2016Publication date: April 13, 2017Inventors: Michael F. Deering, Michael G. Lavelle
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Patent number: 9478001Abstract: A high-speed ring topology. In one embodiment, two base chip types are required: a “drawing” chip, LoopDraw, and an “interface” chip, LoopInterface. Each of these chips have a set of pins that supports an identical high speed point to point unidirectional input and output ring interconnect interface: the LoopLink. The LoopDraw chip uses additional pins to connect to several standard memories that form a high bandwidth local memory sub-system. The LoopInterface chip uses additional pins to support a high speed host computer host interface, at least one video output interface, and possibly also additional non-local interconnects to other LoopInterface chip(s).Type: GrantFiled: November 5, 2013Date of Patent: October 25, 2016Assignee: GULA CONSULTING LIMITED LIABILITY COMPANYInventors: Michael F. Deering, Michael G. Lavelle
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Patent number: 9210474Abstract: In some embodiments, an apparatus includes interface circuitry to receive signals including video signals and drawing commands, and a command interpreter to receive the drawing commands and provide on screen display (OSD) signals in response to the drawing commands. Video processing circuitry processes the received video signals to provide processed video signals, and a blender to blend the OSD signals and the processed video signals to produce blended video signals including the OSD signals and the processed video signals. Other embodiments are described and claimed.Type: GrantFiled: November 1, 2013Date of Patent: December 8, 2015Assignee: Lattice Semiconductor CorporationInventors: James G. Hanko, Michael G. Lavelle, J. Duane Northcutt, Brian K. Schmidt
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Publication number: 20140059616Abstract: In some embodiments, an apparatus includes interface circuitry to receive signals including video signals and drawing commands, and a command interpreter to receive the drawing commands and provide on screen display (OSD) signals in response to the drawing commands. Video processing circuitry processes the received video signals to provide processed video signals, and a blender to blend the OSD signals and the processed video signals to produce blended video signals including the OSD signals and the processed video signals. Other embodiments are described and claimed.Type: ApplicationFiled: November 1, 2013Publication date: February 27, 2014Applicant: Silicon Image, Inc.Inventors: James G. Hanko, Michael G. Lavelle, J. Duane Northcutt, Brian K. Schmidt
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Publication number: 20140055485Abstract: A high-speed ring topology. In one embodiment, two base chip types are required: a “drawing” chip, LoopDraw, and an “interface” chip, LoopInterface. Each of these chips have a set of pins that supports an identical high speed point to point unidirectional input and output ring interconnect interface: the LoopLink. The LoopDraw chip uses additional pins to connect to several standard memories that form a high bandwidth local memory sub-system. The LoopInterface chip uses additional pins to support a high speed host computer host interface, at least one video output interface, and possibly also additional non-local interconnects to other LoopInterface chip(s).Type: ApplicationFiled: November 5, 2013Publication date: February 27, 2014Applicant: ALANDRO CONSULTING NY LLCInventors: Michael F. Deering, Michael G. Lavelle
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Patent number: 8599315Abstract: In some embodiments, an apparatus includes interface circuitry to receive signals including video signals and drawing commands, and a command interpreter to receive the drawing commands and provide on screen display (OSD) signals in response to the drawing commands. Video processing circuitry processes the received video signals to provide processed video signals, and a blender to blend the OSD signals and the processed video signals to produce blended video signals including the OSD signals and the processed video signals. Other embodiments are described and claimed.Type: GrantFiled: July 25, 2007Date of Patent: December 3, 2013Assignee: Silicon Image, Inc.Inventors: James G. Hanko, Michael G. Lavelle, J. Duane Northcutt, Brian K. Schmidt
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Patent number: 8593468Abstract: A high-speed ring topology. In one embodiment, two base chip types are required: a “drawing” chip, LoopDraw, and an “interface” chip, LoopInterface. Each of these chips have a set of pins that supports an identical high speed point to point unidirectional input and output ring interconnect interface: the LoopLink. The LoopDraw chip uses additional pins to connect to several standard memories that form a high bandwidth local memory sub-system. The LoopInterface chip uses additional pins to support a high speed host computer host interface, at least one video output interface, and possibly also additional non-local interconnects to other LoopInterface chip(s).Type: GrantFiled: October 5, 2010Date of Patent: November 26, 2013Assignee: Alandro Consulting NY LLCInventors: Michael F. Deering, Michael G. Lavelle
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Patent number: 8311126Abstract: A system including a receiver, a TMDS link (or other serial link), and a transmitter configured to transmit K-bit video words (typically, encoded 8-bit video words) over the link. In typical embodiments, the transmitter is configured to pack a sequence of N-bit video words, where N?K (e.g., N=10, 12, or 16, when K=8) into a sequence of K-bit fragments, encode the fragments, and transmit the encoded fragments. The transmitted data are indicative of a sequence of M-fragment groups, and the transmitter is typically configured also to transmit over the link packing phase data indicative of the phase of the most recently transmitted fragment. Other aspects are transmitters and receivers for use in such a system and methods implemented by any such transmitter, receiver, or system.Type: GrantFiled: July 13, 2009Date of Patent: November 13, 2012Assignee: Silicon Image, Inc.Inventors: Michael G. Lavelle, Paul Daniel Wolf
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Publication number: 20110221742Abstract: A high-speed ring topology. In one embodiment, two base chip types are required: a “drawing” chip, LoopDraw, and an “interface” chip, LoopInterface. Each of these chips have a set of pins that supports an identical high speed point to point unidirectional input and output ring interconnect interface: the LoopLink. The LoopDraw chip uses additional pins to connect to several standard memories that form a high bandwidth local memory sub-system. The LoopInterface chip uses additional pins to support a high speed host computer host interface, at least one video output interface, and possibly also additional non-local interconnects to other LoopInterface chip(s).Type: ApplicationFiled: October 5, 2010Publication date: September 15, 2011Inventors: Michael F. Deering, Michael G. Lavelle
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Patent number: 7808505Abstract: A high-speed ring topology. In one embodiment, two base chip types are required: a “drawing” chip, LoopDraw, and an “interface” chip, LoopInterface. Each of these chips have a set of pins that supports an identical high speed point to point unidirectional input and output ring interconnect interface: the LoopLink. The LoopDraw chip uses additional pins to connect to several standard memories that form a high bandwidth local memory sub-system. The LoopInterface chip uses additional pins to support a high speed host computer host interface, at least one video output interface, and possibly also additional non-local interconnects to other LoopInterface chip(s).Type: GrantFiled: May 27, 2008Date of Patent: October 5, 2010Inventors: Michael F. Deering, Michael G. Lavelle
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Publication number: 20090274218Abstract: A system including a receiver, a TMDS link (or other serial link), and a transmitter configured to transmit K-bit video words (typically, encoded 8-bit video words) over the link. In typical embodiments, the transmitter is configured to pack a sequence of N-bit video words, where N?K (e.g., N=10, 12, or 16, when K=8) into a sequence of K-bit fragments, encode the fragments, and transmit the encoded fragments. The transmitted data are indicative of a sequence of M-fragment groups, and the transmitter is typically configured also to transmit over the link packing phase data indicative of the phase of the most recently transmitted fragment. Other aspects are transmitters and receivers for use in such a system and methods implemented by any such transmitter, receiver, or system.Type: ApplicationFiled: July 13, 2009Publication date: November 5, 2009Applicant: SILICON IMAGE, INC.Inventors: Michael G. Lavelle, Paul Daniel Wolf
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Patent number: 7599439Abstract: A system including a receiver, a TMDS link (or other serial link), and a transmitter configured to transmit K-bit video words (typically, encoded 8-bit video words) over the link. In typical embodiments, the transmitter is configured to pack a sequence of N-bit video words, where N?K (e.g., N=10, 12, or 16, when K=8) into a sequence of K-bit fragments, encode the fragments, and transmit the encoded fragments. The transmitted data are indicative of a sequence of M-fragment groups, and the transmitter is typically configured also to transmit over the link packing phase data indicative of the phase of the most recently transmitted fragment. Other aspects are transmitters and receivers for use in such a system and methods implemented by any such transmitter, receiver, or system.Type: GrantFiled: June 24, 2005Date of Patent: October 6, 2009Assignee: Silicon Image, Inc.Inventors: Michael G. Lavelle, Paul Daniel Wolf
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Patent number: 7502470Abstract: In a class of embodiments, the invention is an open computing system (e.g., a PC) in which a protected, closed subsystem is embedded. The closed subsystem typically includes multiple parts that ensure that content protection keys and protected content are never revealed outside the closed subsystem. Content (e.g., high-definition digital video) that enters the closed subsystem (and is typically decrypted and re-encrypted within the closed subsystem) is afforded a similar level of protection within the open system as can be obtained in standalone closed systems. Other aspects of the invention are methods for protecting content within an open computing system, a closed system (or disk drive thereof) configured to be embedded in an open computing system, and circuitry configured to be embedded in an open computing system for combining the output of a closed subsystem with other output (e.g., graphics and/or audio output) of the open computing system.Type: GrantFiled: October 3, 2003Date of Patent: March 10, 2009Assignee: Silicon Image, Inc.Inventors: James G. Hanko, Michael G. Lavelle, James D. Lyle, J. Duane Northcutt
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Publication number: 20090027555Abstract: In some embodiments, an apparatus includes interface circuitry to receive signals including video signals and drawing commands, and a command interpreter to receive the drawing commands and provide on screen display (OSD) signals in response to the drawing commands. Video processing circuitry processes the received video signals to provide processed video signals, and a blender to blend the OSD signals and the processed video signals to produce blended video signals including the OSD signals and the processed video signals. Other embodiments are described and claimed.Type: ApplicationFiled: July 25, 2007Publication date: January 29, 2009Inventors: James G. Hanko, Michael G. Lavelle, J. Duane Northcutt, Brian K. Schmidt
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Publication number: 20080266300Abstract: A high-speed ring topology. In one embodiment, two base chip types are required: a “drawing” chip, LoopDraw, and an “interface” chip, LoopInterface. Each of these chips have a set of pins that supports an identical high speed point to point unidirectional input and output ring interconnect interface: the LoopLink. The LoopDraw chip uses additional pins to connect to several standard memories that form a high bandwidth local memory sub-system. The LoopInterface chip uses additional pins to support a high speed host computer host interface, at least one video output interface, and possibly also additional non-local interconnects to other LoopInterface chip(s).Type: ApplicationFiled: May 27, 2008Publication date: October 30, 2008Inventors: Michael F. Deering, Michael G. Lavelle
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Publication number: 20080148063Abstract: In a class of embodiments, the invention is an open computing system (e.g., a PC) in which a protected, closed subsystem is embedded. The closed subsystem typically includes multiple parts that ensure that content protection keys and protected content are never revealed outside the closed subsystem. Content (e.g., high-definition digital video) that enters the closed subsystem (and is typically decrypted and re-encrypted within the closed subsystem) is afforded a similar level of protection within the open system as can be obtained in standalone closed systems. Other aspects of the invention are methods for protecting content within an open computing system, a closed system (or disk drive thereof) configured to be embedded in an open computing system, and circuitry configured to be embedded in an open computing system for combining the output of a closed subsystem with other output (e.g., graphics and/or audio output) of the open computing system.Type: ApplicationFiled: October 3, 2003Publication date: June 19, 2008Inventors: James G. Hanko, Michael G. Lavelle, James D. Lyle, J. Duane Northcutt
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Patent number: 7379067Abstract: A high-speed ring topology. In one embodiment, two base chip types are required: a “drawing” chip, LoopDraw, and an “interface” chip, LoopInterface. Each of these chips have a set of pins that supports an identical high speed point to point unidirectional input and output ring interconnect interface: the LoopLink. The LoopDraw chip uses additional pins to connect to several standard memories that form a high bandwidth local memory sub-system. The LoopInterface chip uses additional pins to support a high speed host computer host interface, at least one video output interface, and possibly also additional non-local interconnects to other LoopInterface chip(s).Type: GrantFiled: December 15, 2005Date of Patent: May 27, 2008Inventors: Michael F. Deering, Michael G. Lavelle
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Patent number: 7145570Abstract: A system and a method for improving magnified texture-mapped pixel performance in a single-pixel pipeline. A plurality of textured pixel addresses corresponding to a plurality of pixels may be generated. A FIFO or other memory unit may be used to linearly order the plurality of textured pixel addresses. Two consecutive textured pixel addresses out of the plurality of textured pixel addresses may be examined if they map to a common set of texels in texture space. The two consecutive textured pixel addresses may be merged together and propagated down the pipeline if they map to the common set of texels. However, only a first of the two consecutive textured pixel addresses may be propagated down the pipeline if the two consecutive textured pixel addresses do not map to a common set of texels. Texel data may be generated in response to receiving either the combined texel structure or the first of the two textured pixel addresses.Type: GrantFiled: December 12, 2002Date of Patent: December 5, 2006Assignee: Sun Microsystems, Inc.Inventors: Brian D. Emberling, Michael G. Lavelle
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Patent number: 7129941Abstract: A system and method are disclosed for rendering polygons. Parameter values may be rendered for only one sample position of a plurality of neighboring sample positions within a polygon. The parameter values rendered for the one sample position may then be transmitted to one or more memories and conditionally stored in a plurality of memory locations that correspond to the plurality of neighboring sample positions. Transmitting parameter values to one or more memories may be achieved in a single transaction. Depth values may be rendered for each sample position in the plurality of neighboring sample positions. Depth value data may be compressed. In some embodiments, the one or more memories may be configured to determine depth values for each of the neighboring sample positions.Type: GrantFiled: March 19, 2003Date of Patent: October 31, 2006Assignee: Sun Microsystems, Inc.Inventors: Michael F. Deering, Michael G. Lavelle