Abstract: A system and a method for improving magnified texture-mapped pixel performance in a single-pixel pipeline. A plurality of textured pixel addresses corresponding to a plurality of pixels may be generated. A FIFO or other memory unit may be used to linearly order the plurality of textured pixel addresses. Two consecutive textured pixel addresses out of the plurality of textured pixel addresses may be examined if they map to a common set of texels in texture space. The two consecutive textured pixel addresses may be merged together and propagated down the pipeline if they map to the common set of texels. However, only a first of the two consecutive textured pixel addresses may be propagated down the pipeline if the two consecutive textured pixel addresses do not map to a common set of texels. Texel data may be generated in response to receiving either the combined texel structure or the first of the two textured pixel addresses.

Abstract: A system and method for preserving the order of data items through a divergence-and-reconvergence of two or more paths in a hardware device. A host processor may write a first token to a first path in the hardware device. A convergence unit in the hardware device may receive and store the first token in a synchronization register. The host processor may poll the synchronization register to determine when the first token arrives in the synchronization register. In response to determining that the first token has arrived in the synchronization register, the host processor may safely write a sequence of one or more data items to a second path in the hardware device.

Abstract: One embodiment of a method of performing a font operation involves receiving a set of font data identifying a font operation to be performed. If a first font data unit in the set indicates that a first coordinate should be a background color and transparent background is enabled, the method involves outputting an enable for a second font data unit in the set. The second font data unit indicates that a second coordinate should be a foreground color. The enable for the second coordinate is output instead of a disable for the first coordinate. If instead the first font data unit in the set indicates that the first coordinate should be a background color and transparent background is disabled, the method may involve outputting a disable for the first coordinate.

Abstract: A system and method are disclosed for utilizing a Z slope test to select polygons that may be candidates for multiple storage methods. The method may calculate the absolute Z slope from vertex data and compare the calculated value with a specified threshold value. In some embodiments, for polygons that have an absolute Z slope less than the threshold value, parameter values may be rendered for only one sample position of multiple neighboring sample positions. The parameter values rendered for the one sample position may then be stored in multiple memory locations that correspond to the multiple neighboring sample positions. In some embodiments, storing parameter values in multiple memory locations may be achieved in a single write transaction. In some embodiments, utilization of the Z slope test method may be subject to user input and in other embodiments may be a dynamic decision controlled by the graphics system.

Abstract: A graphics system may include a frame buffer that includes several sets of one or more memory banks and a cache. The frame buffer may load data from one of the memory banks into the cache in response to receiving a cache fill request. Each set of memory banks is accessible independently of each other set of memory banks. A frame buffer interface coupled to the frame buffer includes a plurality of cache fill request queues. Each cache fill request queue is configured to store one or more cache fill requests targeting a corresponding one of the sets of memory banks. The frame buffer interface is configured to select a cache fill request from one of the cache fill request queues that stores cache fill requests targeting a set of memory banks that is not currently being accessed and to provide the selected cache fill request to the frame buffer.

Abstract: A graphics system and method for storing pixel values into or reading pixel values from a sample buffer, wherein the sample buffer is configured to store a plurality of samples for each of a plurality of pixels. The graphics system comprises a sample buffer, a programmable register, and a graphics processor. The programmable register stores a value indicating a method for pixel to sample conversion, and is preferably software programmable (e.g., user programmable). The graphics processor accesses the memory to determine a method for pixel to sample conversion and stores the pixel values in the sample buffer according to the determined method. A first method for pixel to sample conversion may specify a pixel write to all of the pixel's supporting samples. A second method for pixel to sample conversion may specify a pixel write to a selected one of the pixel's supporting samples.

Abstract: A system for dynamic blending of an image into an accumulation buffer. The blending system may include an accumulation buffer, an image buffer, and a mixing unit. The mixing unit may be configured to read a stream of image pixels from the image buffer, to read a stream of corresponding pixels from the accumulation buffer, to blend each image pixel with the corresponding accumulation buffer pixel based on an alpha value provided with the image pixel, and thus, generate a stream of output pixels. The stream of output pixels may be returned to the accumulation buffer. The color depth precision of the accumulation buffer may be larger than the color depth precision of the image buffer.

Abstract: An external cache management unit for use with 3D-RAM and suitable for use in a computer graphics system is described. The unit maintains and tracks the status of level one cache memory in the 3D-RAM. The unit identifies dirty blocks of cache memory and prioritizes block cleansing based on a least used algorithm. Periodic block cleansing during empty memory cycles is provided for, and may also be prompted on demand.

Abstract: A programmable filter comprising a tree of computational units, where each computational unit is configured to receive multiple inputs and generate multiple outputs, where the tree receives a set of input operands and generates output operands, where, in a sum of products mode, the output operands of the tree comprise a sum of products of the input operands by corresonding N-bit coefficients, where N is a positive integer, where, in a linear interpolation mode, each of the output operands of the tree comprise linear interpolations of at least two of the input operands, wherein coefficients of the linear interpolations have (N/2) bits of precision.

Abstract: A system and method for assigning operations to multiple pipelines in a graphics system is disclosed. The graphics system may include an arbitration unit coupled to a plurality of calculation pipelines. The arbitration unit is operable to provide graphics operations to selected ones of the calculation pipelines. Each of the calculation pipelines is operable to perform a graphics operation. Each of the calculation pipelines may include digital logic and/or a processing element for performing the graphics operations. An operation may be assigned to a pipeline if the pipeline is performing a low latency operation. A low latency operation may comprise an operation that is performed by one of the calculation pipelines in less time than a pre-determined number of clock cycles.

Abstract: A system and method for rendering a polygon, such as a triangle. The method may comprise receiving geometry data (or vertex data) defining vertices of the polygon. The method may compute initial vertex x,y values at end points proximate to each of the vertices of the polygon, and a slope value along each edge of the polygon. The computed slope may be a quantized slope value having a first number of bits of precision. The first number of bits of precision may produce inaccuracies for interpolated x,y values computed at the end points of an edge of the polygon. The method may then interpolate x,y values along each respective edge of the polygon using the computed slope along the respective edge of the polygon. Finally the method may store final x,y values for each respective edge of the polygon. The final x,y values comprise the interpolated x,y values for non-end points of the respective edge, and the computed initial vertex x,y values for each of the end points of the respective edge.

Abstract: A graphics system and method for processing geometry compressed, three-dimensional graphics data are disclosed. After transforming and lighting each vertex, a vertex data stream is decompressed using connectivity information, and vertexes are reassembled into geometric primitives. The connectivity information may include mesh buffer references, vertex tags, or other types of information. Independent buffers, queues, and/or caches are used to simultaneously store: (a) vertex data for the next several primitives, (b) vertex data that will be reused, (c) vertex tags, (d) control tags, (e) vertex data being assembled into a primitive, and (f) an assembled primitive ready to be launched. The assembled primitive may be clip tested for visibility in a defined viewport, before investing time to have the primitive processed into pixel data for display. The independent buffers, queues, and/or caches may also enable the vertex processing steps to be performed in parallel and at different rates.

Abstract: A data queue optimized for receiving loosely packed graphics data and suitable for use in a computer graphics system is described. The data queue operates on first-in-first-out principals, and has a variable width input and output. The variable width on the input side facilitates the reception and storage of loosely packed data. The variable width output allows for the single-cycle output of multi-word data. Packing of the data occurs on the write-side of the FIFO structure.

Abstract: An optimizing unit for use with an interleaved memory and suitable for use in a computer graphics system is described. The unit utilizes knowledge of the repetitive and predictable nature of texture buffer accesses to potentially reduce the number of memory fetches. The unit maintains a queue of pending requests for tiles of data from the memory, and predicts the retrieval of redundant data within short sequences of requests. The redundant data is retrieved from the memory once, and repeated as necessary from local temporary storage registers.

Abstract: A graphics system comprising a programmable sample buffer and a sample buffer interface. The sample buffer interface is configured to (a) buffer N streams of samples in N corresponding input buffers, wherein N is greater than or equal to two, (b) store N sets of context values corresponding to the N input buffers respectively, (c) terminate transfer of samples from a first of the input buffers to the programmable sample buffer, (d) selectively update a subset of state registers in the programmable sample buffer with context values corresponding to a next input buffer of the input buffers, (e) initiate transfer of samples from the next input buffer to the programmable sample buffer. The context values stored in the state registers of the programmable sample buffer determine the operation of an arithmetic logic unit internal to the programmable sample buffer on samples data.

Abstract: A graphics system configured to apply multiple layers of texture information to batches of primitives. The graphics system collects primitives into a batch that share a common set of texture layers to be applied. The batch is limited so that the total estimate size of the batch is less than or equal to a storage capacity of a texture accumulation buffer. The graphics system stores samples (or fragments) corresponding to the batch primitives in the texture accumulation buffer between the application of successive texture layers.

Abstract: A memory interface controls read and write accesses to a memory device. The memory device includes a level-one cache, level-two cache and storage cell array. The memory interface includes a data request processor (DRP), a memory control processor (MCP) and a block cleansing unit (BCU). The MCP controls transfers between the storage cell array, the level-two cache and the level-one cache. In response to a read request with associated read clear indication, the DRP controls a read from a level-one cache block, updates bits in a corresponding dirty tag, and sets a mode indicator of the dirty tag to a the read clear mode. The modified dirty tag bits and mode indicator are signals to the BCU that the level-one cache block requires a source clear operation. The BCU commands the transfer of data from a color fill block in the level-one cache to the level-two cache.

Abstract: A graphics system that is configured to synchronize a slave display channel to a master display channel may include a master display timing generator configured to provide a frame event indication and a slave display timing generator. The slave display timing generator may be configured to receive the frame event indication and, in response to receiving the frame event indication during its active display period, the slave display timing generator may be configured to wait until its current active display period ends and then jump to its synchronization point. Alternatively, the slave display timing generator may be configured to jump to its synchronization point immediately or after the end of the current horizontal line, and any remaining display information in an interrupted frame may be displayed during the next active display period.

Abstract: A graphics system includes a frame buffer, a write address generator, and a pixel buffer. A burst of pixels received from the frame buffer may not be in display order. In one embodiment, a write address generator calculates a write address for each pixel in the burst of pixels output from the frame buffer. The write address corresponds to a relative display order within the burst for each respective pixel. Each pixel in the burst is stored to its write address in the pixel buffer. This way, the pixels in the burst are stored in display order within the pixel buffer.

Abstract: A system and method for rasterizing and rendering graphics data is disclosed. Vertices may be grouped to form primitives such as triangles, which are rasterized using two-dimensional arrays of samples bins. To overcome fragmentation problems, the system's sample evaluation hardware may be configured to over-evaluate samples each clock cycle. Since a number of the samples will typically not survive evaluation because they will be outside the primitive being rendered, the remaining surviving samples may be combined into sets, with one set being forwarded to subsequent pipeline stages each clock cycle in order to attempt to keep the pipeline utilization high.