Abstract: A graphics system includes a frame buffer that includes one or more memory devices and a frame buffer interface coupled to the frame buffer. Each memory device in the frame buffer includes N banks. Each of the N banks includes multiple pages, and each page is configured to store data corresponding to a portion of a screen region. The frame buffer interface is configured to generate address used to store data corresponding to a frame of data in the frame buffer. The frame includes multiple screen regions. The frame buffer interface is configured to generate addresses corresponding to the data and to provide the addresses to the frame buffer. The addresses are generated such that each of the N banks stores data corresponding to a portion of one out of every N screen regions within a horizontal group of screen regions.

Abstract: A graphics system includes a frame buffer, a write address generator, and a pixel buffer. A burst of pixels received from the frame buffer may not be in display order. In one embodiment, a write address generator calculates a write address for each pixel in the burst of pixels output from the frame buffer. The write address corresponds to a relative display order within the burst for each respective pixel. Each pixel in the burst is stored to its write address in the pixel buffer. This way, the pixels in the burst are stored in display order within the pixel buffer.

Abstract: One embodiment of a method of performing a font operation involves receiving a set of font data identifying a font operation to be performed. If a first font data unit in the set indicates that a first coordinate should be a background color and transparent background is enabled, the method involves outputting an enable for a second font data unit in the set. The second font data unit indicates that a second coordinate should be a foreground color. The enable for the second coordinate is output instead of a disable for the first coordinate. If instead the first font data unit in the set indicates that the first coordinate should be a background color and transparent background is disabled, the method may involve outputting a disable for the first coordinate.

Abstract: A graphics system and method for storing pixel values into or reading pixel values from a sample buffer, wherein the sample buffer is configured to store a plurality of samples for each of a plurality of pixels. The graphics system comprises a sample buffer, a programmable register, and a graphics processor. The programmable register stores a value indicating a method for pixel to sample conversion, and is preferably software programmable (e.g., user programmable). The graphics processor accesses the memory to determine a method for pixel to sample conversion and stores the pixel values in the sample buffer according to the determined method. A first method for pixel to sample conversion may specify a pixel write to all of the pixel's supporting samples. A second method for pixel to sample conversion may specify a pixel write to a selected one of the pixel's supporting samples.

Abstract: A graphics system and method for processing geometry compressed, three-dimensional graphics data are disclosed. After transforming and lighting each vertex, a vertex data stream is decompressed using connectivity information, and vertexes are reassembled into geometric primitives. The connectivity information may include mesh buffer references, vertex tags, or other types of information. Independent buffers, queues, and/or caches are used to simultaneously store: (a) vertex data for the next several primitives, (b) vertex data that will be reused, (c) vertex tags, (d) control tags, (e) vertex data being assembled into a primitive, and (f) an assembled primitive ready to be launched. The assembled primitive may be clip tested for visibility in a defined viewport, before investing time to have the primitive processed into pixel data for display. The independent buffers, queues, and/or caches may also enable the vertex processing steps to be performed in parallel and at different rates.

Abstract: An optimizing unit for use with an interleaved memory and suitable for use in a computer graphics system is described. The unit utilizes knowledge of the repetitive and predictable nature of texture buffer accesses to potentially reduce the number of memory fetches. The unit maintains a queue of pending requests for tiles of data from the memory, and predicts the retrieval of redundant data within short sequences of requests. The redundant data is retrieved from the memory once, and repeated as necessary from local temporary storage registers.

Abstract: A graphics system may include a frame buffer that includes several sets of one or more memory banks and a cache. The frame buffer may load data from one of the memory banks into the cache in response to receiving a cache fill request. Each set of memory banks is accessible independently of each other set of memory banks. A frame buffer interface coupled to the frame buffer includes a plurality of cache fill request queues. Each cache fill request queue is configured to store one or more cache fill requests targeting a corresponding one of the sets of memory banks. The frame buffer interface is configured to select a cache fill request from one of the cache fill request queues that stores cache fill requests targeting a set of memory banks that is not currently being accessed and to provide the selected cache fill request to the frame buffer.

Abstract: A graphics system may include a frame buffer, a processing device coupled to access data in the frame buffer, a frame buffer interface coupled to the frame buffer, and an output controller configured to assert a request for display data to provide to a display device. The frame buffer interface may receive the request for display data from the output controller and delay providing the request for display data to the frame buffer if the processing device is currently requesting access to a portion of the frame buffer targeted by the request for display data. For example, if the frame buffer includes several memory banks and the request for display data targets a first bank, the frame buffer interface may delay providing the request for display data to the frame buffer if the processing device is currently requesting access to the first bank.

Abstract: A system and method for rasterizing and rendering graphics data is disclosed. Vertices may be grouped to form primitives such as triangles, which are rasterized using two-dimensional arrays of samples bins. Individual samples may be selected from the bins according to different criteria such as memory bank allocation to improve utilization of the system's rendering pipeline. Since the arrays may have more bins than the number of evaluation units in the rendering pipeline, the samples from the bins may be stored to FIFO memories to allow invalid or empty samples (those outside the primitive being rendered) to be removed. The samples may then be filtered to form pixels that are displayable to form an image on a display device.

Abstract: A rendering unit positions a supertile so that it intersects a primitive. The rendering unit repeatedly walks over bins of the supertile, applying a layer of texture to the bins of the supertile in each iteration of said repeated walking. The rendering unit advances to the next texture layer after having applied the current texture layer to each candidate bin of the supertile. The results of each texture layer application to the bins may be stored in a texture accumulation buffer. The size of the supertile corresponds to the size of the texture accumulation buffer. After applying a last layer of texture to the bins of the supertile, the supertile may be advanced to a new position. The rendering unit traverses the primitive with the supertile so that the union of areas visited by the supertile covers the primitive.

Abstract: A system and method are disclosed for rendering polygons. Parameter values may be rendered for only one sample position of a plurality of neighboring sample positions within a polygon. The parameter values rendered for the one sample position may then be transmitted to one or more memories and conditionally stored in a plurality of memory locations that correspond to the plurality of neighboring sample positions. Transmitting parameter values to one or more memories may be achieved in a single transaction. Depth values may be rendered for each sample position in the plurality of neighboring sample positions. Depth value data may be compressed. In some embodiments, the one or more memories may be configured to determine depth values for each of the neighboring sample positions.

Abstract: A system and method capable of super-sampling and performing super-sample convolution are disclosed. In one embodiment, the system may comprise a graphics processor, a frame buffer, a sample cache, and a sample-to-pixel calculation unit. The graphics processor may be configured to generate a plurality of samples. The frame buffer, which is coupled to the graphics processor, may be configured to store the samples in a sample buffer. The samples may be positioned according to a regular grid, a perturbed regular grid, or a stochastic grid. The sample-to-pixel calculation unit is programmable to select a variable number of stored samples from the frame buffer, copy the selected samples to a sample cache, and filter a set of the selected samples into an output pixel. The sample-to-pixel calculation unit retains those samples in the sample cache that will be reused in a subsequent pixel calculation and replaces those samples no longer required with new samples for another filter calculation.

Abstract: A graphics system configured to apply multiple layers of texture information to batches of primitives. The graphics system collects primitives into a batch that share a common set of texture layers to be applied. The batch is limited so that the total estimate size of the batch is less than or equal to a storage capacity of a texture accumulation buffer. The graphics system stores samples (or fragments) corresponding to the batch primitives in the texture accumulation buffer between the application of successive texture layers.

Abstract: A memory interface controls read and write accesses to a memory device. The memory device includes a level-one cache, level-two cache and storage cell array. The memory interface includes a data request processor (DRP), a memory control processor (MCP) and a block cleansing unit (BCU). The MCP controls transfers between the storage cell array, the level-two cache and the level-one cache. In response to a read request with associated read clear indication, the DRP controls a read from a level-one cache block, updates bits in a corresponding dirty tag, and sets a mode indicator of the dirty tag to a the read clear mode. The modified dirty tag bits and mode indicator are signals to the BCU that the level-one cache block requires a source clear operation. The BCU commands the transfer of data from a color fill block in the level-one cache to the level-two cache.

Abstract: The method for line patterning may include receiving line data for a first line. The line data for the first line may include an original starting point and an original endpoint. The first line may be divided into one or more line segments, which may include generating a new starting point and a new endpoint for one or more of the one or more line segments. The new line segments may then be rasterized from the new endpoint to the new starting point. In other words, each line segment may be rasterized from right to left, thus avoiding problems associated with multiple consecutive accesses of pixel addresses in the pixel buffer. The original or intended line pattern of the line is preserved since the zeros and ones are drawn or rendered in their appropriate locations as if they were being drawn left to right, even though they are actually rasterized from right to left.

Abstract: A graphical processing system comprising a computational unit and a shadow processing unit coupled to the computational unit through a communication bus. The computational unit is configured to transfer coordinates C1 of a point P with respect to a first space to the shadow processing unit. In response to receiving the coordinates C1, the shadow processing unit is configured to: (a) transform the coordinate C1 to determine map coordinates s and t and a depth value DP for the point P, (b) access a neighborhood of depth values from a memory using the map coordinates s and t, (c) compare the depth value DP to the depth values of the neighborhood, (d) filter binary results of the comparisons to determine a shadow fraction, and (e) transfer the shadow fraction to the computational unit through the communication bus.

Abstract: A graphics system configured to operate on a collection of vertices to determine mappings from an initial order to secondary and tertiary ordering. The initial order corresponds to the ordering of the vertices in an input buffer. The secondary (tertiary) ordering corresponds to the ordering of the vertices along a triangle major (minor) axis. The graphics system computes horizontal and vertical displacements along edges of the triangle in the initial ordering, and uses the signs of the horizontal displacements and vertical displacements to access a mapping table which determines the mappings. The mappings may be used to rasterize the triangle in terms of pixels (or samples).

Abstract: A graphics system that is configured to synchronize a slave display channel to a master display channel may include a master display timing generator configured to provide a frame event indication and a slave display timing generator. The slave display timing generator may be configured to receive the frame event indication and, in response to receiving the frame event indication during its active display period, the slave display timing generator may be configured to wait until its current active display period ends and then jump to its synchronization point. Alternatively, the slave display timing generator may be configured to jump to its synchronization point immediately or after the end of the current horizontal line, and any remaining display information in an interrupted frame may be displayed during the next active display period.

Abstract: A computer graphics system that utilizes a super-sampled sample buffer and a sample-to-pixel calculation unit for refreshing the display. The graphics system may have a graphics processor, a super-sampled sample buffer, and a sample-to-pixel calculation unit. The graphics processor renders samples into the sample buffer at computed positions or locations in the sample buffer. The graphics system may utilize a window ID that specifies attributes of pixels on a per object basis. The window ID may specify one or more of a sample mode, filter type, color attributes, or source attributes. The sample mode may include single sample per pixel mode and multiple samples per pixel mode. In implementing a single sample per pixel mode, the graphics system may be further operable to generate a single sample per pixel for certain windows of the screen in order to, for example, provide backwards compatibility with legacy systems with no multi-sampling support.

Abstract: A programmable filter comprising a tree of computational units, where each computational unit is configured to receive multiple inputs and generate multiple outputs, where the tree receives a set of input operands and generates output operands, where, in a sum of products mode, the output operands of the tree comprise a sum of products of the input operands by corresponding N-bit coefficients, where N is a positive integer, where, in a linear interpolation mode, each of the output operands of the tree comprise linear interpolations of at least two of the input operands, wherein coefficients of the linear interpolations have (N/2) bits of precision.