Abstract: Described herein are photonic sources and related system architectures that can satisfy the optical power requirements of large photonic accelerators. Some embodiments relate to a computer comprising a photonic accelerator configured to perform matrix multiplication; a fiber array optically coupled to the photonic accelerator; and a photonic source optically coupled to the fiber array. The photonic source comprising a laser array comprising a plurality of monolithically co-integrated lasers, and a coupling lens array comprising a plurality of monolithically co-integrated lenses, the coupling lens array optically coupling the laser array to the fiber array. The laser array is configured to output between 0.1 W and 10 W of optical power.

Abstract: Systems and methods for performing signed matrix operations using a linear photonic processor are provided. The linear photonic processor is formed as an array of first amplitude modulators and second amplitude modulators, the first amplitude modulators configured to encode elements of a vector into first optical signals and the second amplitude modulators configured to encode a product between the vector elements and matrix elements into second optical signals. An apparatus may be used to implement a signed value of an output of the linear processor. The linear photonic processor may be configured to perform matrix-vector and/or matrix-matrix operations.

Abstract: Systems and methods for performing signed matrix operations using a linear photonic processor are provided. The linear photonic processor is formed as an array of first amplitude modulators and second amplitude modulators, the first amplitude modulators configured to encode elements of a vector into first optical signals and the second amplitude modulators configured to encode a product between the vector elements and matrix elements into second optical signals. An apparatus may be used to implement a signed value of an output of the linear processor. The linear photonic processor may be configured to perform matrix-vector and/or matrix-matrix operations.

Abstract: A nano-opto-electro-mechanical System (NOEMS) phase shifter is described. The NOEMS may include a multi-slot waveguide structure suspended in air. The multi-slot waveguide structure may include three or more waveguides separated from each other by slots. The width of the slots may be sufficiently small to support slot modes, where a substantial portion of the mode energy is within the slots. For example, the slots may have widths less than 200 nm or less than 100 nm. The multi-slot waveguide structure may be disposed in a trench formed though the upper cladding of a substrate. An undercut may be formed under the multi-slot waveguide structure to enable free motion of the structure. NOEMS phase modulators of the types described herein may be used in connection with photonic processing systems, telecom/datacom systems, analog systems, etc.

Abstract: Low-noise optical differential receivers are described. Such differential receivers may include a differential amplifier having first and second inputs and first and second outputs, and four photodetectors. A first and a second of such photodetectors are coupled to the first input of the differential amplifier, and a third and a fourth of such photodetectors are coupled to the second input of the differential amplifier. The anode of the first photodetector and the cathode of the second photodetector are coupled to the first input of the differential amplifier. The cathode of the third photodetector and the anode of the fourth photodetector are coupled to the second input of the differential amplifier. The optical receiver may involve two stages of signal subtraction, which may significantly increase noise immunity.

Abstract: Photonic packages are described. One such photonic package includes a photonic chip, an application specific integrated circuit, and optionally, an interposer. The photonic chip includes photonic microelectromechanical system (MEMS) devices. A photonic package may include a material layer patterned to include recesses. The recesses are aligned with the photonic MEMS devices so as to form enclosed cavities around the photonic MEMS devices. This arrangement preserves the integrity of the photonic MEMS devices.

Abstract: Systems and methods for performing matrix operations using a path-number balanced optical network are provided. The optical network is formed as an array including active optical components and passive optical components arranged at a substantially central location of the array. The optical network includes at least NM active optical components which are used to implement a first matrix of any size N×M by embedding the first matrix in a second matrix of a larger size. The optical network performs matrix-vector and matrix-matrix operations by propagating one or more pluralities of optical signals corresponding to an input vector through the optical network.

Abstract: Systems and methods for increasing throughput of a photonic processor by using photonic degrees of freedom (DOF) are provided. The photonic processor includes a multiplexer configured to multiplex, using at least one photonic DOF, multiple encoded optical signals into a multiplexed optical signal. The photonic processor also includes a detector coupled to an output of an optical path including the multiplexer, the detector being configured to generate a first current based on the multiplexed optical signal or a demultiplexed portion of the multiplexed optical signal. The photonic processor further includes a modulator coupled to and output of the detector, the modulator being configured to generate a second current by modulating the first current.

Abstract: Hybrid analog-digital processing systems are described. An example of a hybrid analog-digital processing system includes photonic accelerator configured to perform matrix-vector multiplication using light. The photonic accelerator exhibits a frequency response having a first bandwidth (e.g., less than 3 GHz). The hybrid analog-digital processing system further includes a plurality of analog-to-digital converters (ADCs) coupled to the photonic accelerator, and a plurality of digital equalizers coupled to the plurality of ADCs, wherein the digital equalizers are configured to set a frequency response of the hybrid analog-digital processing system to a second bandwidth greater than the first bandwidth.

Abstract: Systems and methods for performing matrix operations using a path-number balanced optical network are provided. The optical network is formed as an array including active optical components and passive optical components arranged at a substantially central location of the array. The optical network includes at least NM active optical components which are used to implement a first matrix of any size N×M by embedding the first matrix in a second matrix of a larger size. The optical network performs matrix-vector and matrix-matrix operations by propagating one or more pluralities of optical signals corresponding to an input vector through the optical network.

Abstract: Low-noise optical differential receivers are described. Such differential receivers may include a differential amplifier having first and second inputs and first and second outputs, and four photodetectors. A first and a second of such photodetectors are coupled to the first input of the differential amplifier, and a third and a fourth of such photodetectors are coupled to the second input of the differential amplifier. The anode of the first photodetector and the cathode of the second photodetector are coupled to the first input of the differential amplifier. The cathode of the third photodetector and the anode of the fourth photodetector are coupled to the second input of the differential amplifier. The optical receiver may involve two stages of signal subtraction, which may significantly increase noise immunity.

Abstract: Photonic processors are described. The photonic processors described herein are configured to perform matrix-matrix (e.g., matrix-vector) multiplication. Some embodiments relate to photonic processors arranged according to a dual-rail architecture, in which numeric values are encoded in the difference between a pair optical signals (e.g., in the difference between the powers of the optical signals). Relative to other architectures, these photonic processors exhibit increased immunity to noise. Some embodiments relate to photonic processors including modulatable detector-based multipliers. Modulatable detectors are detectors designed so that the photocurrent can be modulated according to an electrical control signal. Photonic processors designed using modulatable detector-based multipliers are significantly more compact than other types of photonic processors.

Abstract: Photonic processors are described. The photonic processors described herein are configured to perform matrix-matrix (e.g., matrix-vector) multiplication. Some embodiments relate to photonic processors arranged according to a dual-rail architecture, in which numeric values are encoded in the difference between a pair optical signals (e.g., in the difference between the powers of the optical signals). Relative to other architectures, these photonic processors exhibit increased immunity to noise. Some embodiments relate to photonic processors including modulatable detector-based multipliers. Modulatable detectors are detectors designed so that the photocurrent can be modulated according to an electrical control signal. Photonic processors designed using modulatable detector-based multipliers are significantly more compact than other types of photonic processors.

Abstract: Photonic processors are described. The photonic processors described herein are configured to perform matrix multiplications (e.g., matrix vector multiplications). Matrix multiplications are broken down in scalar multiplications and scalar additions. Some embodiments relate to devices for performing scalar additions in the optical domain. One optical adder, for example, includes an interferometer having a plurality of phase shifters and a coherent detector. Leveraging the high-speed characteristics of these optical adders, some processors are sufficiently fast to support clocks in the tens of gigahertz of frequency, which represent a significant improvement over conventional electronic processors.

Abstract: Described herein are photonic communication platforms that can overcome the memory bottleneck problem, thereby enabling scaling of memory capacity and bandwidth well beyond what is possible with conventional computing systems. Some embodiments provide photonic communication platforms that involve use of photonic modules. Each photonic module includes programmable photonic circuits for placing the module in optical communication with other modules based on the needs of a particular application. The architecture developed by the inventors relies on the use of common photomask sets (or at least one common photomask) to fabricate multiple photonic modules in a single wafer. Photonic modules in multiple wafers can be linked together into a communication platform using optical or electronic means.

Abstract: Photonic processors are described. The photonic processors described herein are configured to perform matrix-matrix (e.g., matrix-vector) multiplication. Some embodiments relate to photonic processors arranged according to a dual-rail architecture, in which numeric values are encoded in the difference between a pair optical signals (e.g., in the difference between the powers of the optical signals). Relative to other architectures, these photonic processors exhibit increased immunity to noise. Some embodiments relate to photonic processors including modulatable detector-based multipliers. Modulatable detectors are detectors designed so that the photocurrent can be modulated according to an electrical control signal. Photonic processors designed using modulatable detector-based multipliers are significantly more compact than other types of photonic processors.

Abstract: Described herein are photonic communication platforms that can overcome the memory bottleneck problem, thereby enabling scaling of memory capacity and bandwidth well beyond what is possible with conventional computing systems. Some embodiments provide photonic communication platforms that involve use of photonic modules. Each photonic module includes programmable photonic circuits for placing the module in optical communication with other modules based on the needs of a particular application. The architecture developed by the inventors relies on the use of common photomask sets (or at least one common photomask) to fabricate multiple photonic modules in a single wafer. Photonic modules in multiple wafers can be linked together into a communication platform using optical or electronic means.

Abstract: The techniques described herein relate to methods and apparatus for interferometric modulation. An apparatus includes an interferometric device comprising a first optical path and a second optical path, and at least one Franz-Keldysh (FK) modulator disposed in either the first optical path or the second optical path of the interferometric device. The interferometric device receives input light, wherein a first portion of the input light travels along the first optical path of the interferometric device, and a second portion of the input light travels along the second optical path of the interferometric device. The FK modulator modulates an intensity of either the first portion of the input light or the second portion of the input light.

Abstract: Photonic processors are described. The photonic processors described herein are configured to perform matrix-matrix (e.g., matrix-vector) multiplication. Some embodiments relate to photonic processors arranged according to a dual-rail architecture, in which numeric values are encoded in the difference between a pair optical signals (e.g., in the difference between the powers of the optical signals). Relative to other architectures, these photonic processors exhibit increased immunity to noise. Some embodiments relate to photonic processors including modulatable detector-based multipliers. Modulatable detectors are detectors designed so that the photocurrent can be modulated according to an electrical control signal. Photonic processors designed using modulatable detector-based multipliers are significantly more compact than other types of photonic processors.

Abstract: Photonic processors are described. The photonic processors described herein are configured to perform matrix-matrix (e.g., matrix-vector) multiplication. Some embodiments relate to photonic processors arranged according to a dual-rail architecture, in which numeric values are encoded in the difference between a pair optical signals (e.g., in the difference between the powers of the optical signals). Relative to other architectures, these photonic processors exhibit increased immunity to noise. Some embodiments relate to photonic processors including modulatable detector-based multipliers. Modulatable detectors are detectors designed so that the photocurrent can be modulated according to an electrical control signal. Photonic processors designed using modulatable detector-based multipliers are significantly more compact than other types of photonic processors.