Patents by Inventor Michael Hargrove
Michael Hargrove has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8809178Abstract: One illustrative method disclosed herein includes forming a plurality of spaced-apart trenches in a semiconducting substrate to thereby define a fin structure for the device, forming a local isolation region within each of the trenches, forming a sacrificial gate structure on the fin structure, wherein the sacrificial gate structure comprises at least a sacrificial gate electrode, and forming a layer of insulating material above the fin structure and within the trench above the local isolation region. In this example, the method further includes performing at least one etching process to remove the sacrificial gate structure to thereby define a gate cavity, after removing the sacrificial gate structure, performing at least one etching process to form a recess in the local isolation region, and forming a replacement gate structure that is positioned in the recess in the local isolation region and in the gate cavity.Type: GrantFiled: February 29, 2012Date of Patent: August 19, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Yanxiang Liu, Michael Hargrove, Xiaodong Yang, Hans van Meer, Laegu Kang, Christian Gruensfelder, Srikanth Samavedam
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Publication number: 20140017862Abstract: A method of forming a semiconductor device is provided that includes forming a gate structure on a channel portion of a semiconductor substrate, forming an interlevel dielectric layer over the gate structure, and forming a opening through the interlevel dielectric layer to an exposed surface of the semiconductor substrate containing at least one of the source region and the drain region. A metal semiconductor alloy contact is formed on the exposed surface of the semiconductor substrate. At least one dielectric sidewall spacer is formed on sidewalls of the opening. An interconnect is formed within the opening in direct contact with the metal semiconductor alloy contact.Type: ApplicationFiled: September 17, 2013Publication date: January 16, 2014Applicants: Globalfoundries Inc., International Business Machines CorporationInventors: Jian Yu, Jeffrey B. Johnson, Zhengwen Li, Chengwen Pei, Michael Hargrove
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Patent number: 8569810Abstract: A method of forming a semiconductor device is provided that includes forming a gate structure on a channel portion of a semiconductor substrate, forming an interlevel dielectric layer over the gate structure, and forming a opening through the interlevel dielectric layer to an exposed surface of the semiconductor substrate containing at least one of the source region and the drain region. A metal semiconductor alloy contact is formed on the exposed surface of the semiconductor substrate. At least one dielectric sidewall spacer is formed on sidewalls of the opening. An interconnect is formed within the opening in direct contact with the metal semiconductor alloy contact.Type: GrantFiled: December 7, 2010Date of Patent: October 29, 2013Assignees: International Business Machines Corporation, GLOBALFOUNDRIES, Inc.Inventors: Jian Yu, Jeffrey B. Johnson, Zhengwen Li, Chengwen Pei, Michael Hargrove
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Publication number: 20130248985Abstract: Disclosed herein are various methods of forming replacement gate structures with a recessed channel region. In one example, the method includes forming a sacrificial gate structure above a semiconducting substrate, removing the sacrificial gate structure to thereby define an initial gate opening having sidewalls and to expose a surface of the substrate and performing an etching process on the exposed surface of the substrate to define a recessed channel in the substrate. The method includes the additional steps of forming a sidewall spacer within the initial gate opening on the sidewalls of the initial gate opening to thereby define a final gate opening and forming a replacement gate structure in the final gate opening.Type: ApplicationFiled: March 26, 2012Publication date: September 26, 2013Applicant: GLOBALFOUNDRIES INC.Inventors: Kuldeep Amarnath, Michael Hargrove, Srikanth Samavedam
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Publication number: 20130224945Abstract: One illustrative method disclosed herein includes forming a plurality of spaced-apart trenches in a semiconducting substrate to thereby define a fin structure for the device, forming a local isolation region within each of the trenches, forming a sacrificial gate structure on the fin structure, wherein the sacrificial gate structure comprises at least a sacrificial gate electrode, and forming a layer of insulating material above the fin structure and within the trench above the local isolation region. In this example, the method further includes performing at least one etching process to remove the sacrificial gate structure to thereby define a gate cavity, after removing the sacrificial gate structure, performing at least one etching process to form a recess in the local isolation region, and forming a replacement gate structure that is positioned in the recess in the local isolation region and in the gate cavity.Type: ApplicationFiled: February 29, 2012Publication date: August 29, 2013Applicant: GLOBALFOUNDRIES Inc.Inventors: Yanxiang Liu, Michael Hargrove, Xiaodong Yang, Hans Van Meer, Laegu Kang, Christian Gruensfelder, Srikanth Samavedam
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Patent number: 8373228Abstract: A method of fabricating a semiconductor device with back side conductive plugs is provided here. The method begins by forming a gate structure overlying a semiconductor-on-insulator (SOI) substrate. The SOI substrate has a support layer, an insulating layer overlying the support layer, an active semiconductor region overlying the insulating layer, and an isolation region outboard of the active semiconductor region. A first section of the gate structure is formed overlying the isolation region and a second section of the gate structure is formed overlying the active semiconductor region. The method continues by forming source/drain regions in the active semiconductor region, and thereafter removing the support layer from the SOI substrate. Next, the method forms conductive plugs for the gate structure and the source/drain regions, where each of the conductive plugs passes through the insulating layer.Type: GrantFiled: January 14, 2010Date of Patent: February 12, 2013Assignee: GLOBALFOUNDRIES, Inc.Inventors: Bin Yang, Rohit Pal, Michael Hargrove
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Patent number: 8294211Abstract: A method of fabricating a semiconductor device with back side conductive plugs is provided here. The method begins by forming a gate structure overlying a semiconductor-on-insulator (SOI) substrate. The SOI substrate has a support layer, an insulating layer overlying the support layer, an active semiconductor region overlying the insulating layer, and an isolation region outboard of the active semiconductor region. A first section of the gate structure is formed overlying the isolation region and a second section of the gate structure is formed overlying the active semiconductor region. The method continues by forming source/drain regions in the active semiconductor region, and thereafter removing the support layer from the SOI substrate. Next, the method forms conductive plugs for the gate structure and the source/drain regions, where each of the conductive plugs passes through the insulating layer.Type: GrantFiled: January 14, 2010Date of Patent: October 23, 2012Assignee: GLOBALFOUNDRIES, Inc.Inventors: Bin Yang, Rohit Pal, Michael Hargrove
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Patent number: 8217463Abstract: Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods are provided. Methods for fabricating a semiconductor device include providing a semiconductor substrate having an active region and a shallow trench isolation (STI) region. Epitaxial layer is formed on the active region to define a lateral overhang portion in a divot at the active region/STI region interface. A gate stack is formed having a first gate stack-forming layer overlying the semiconductor substrate. First gate stack-forming layer includes a non-conformal layer of metal gate-forming material which is directionally deposited to form a thinned break portion just below the lateral overhang portion. After the step of forming the gate stack, a first portion of the non-conformal layer is in the gate stack and a second portion is exposed. The thinned break portion at least partially isolates the first and second portions during subsequent etch chemistries.Type: GrantFiled: February 4, 2011Date of Patent: July 10, 2012Assignee: GLOBALFOUNDRIES Inc.Inventors: Rohit Pal, Michael Hargrove, Frank Bin Yang
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Publication number: 20120139015Abstract: A method of forming a semiconductor device is provided that includes forming a gate structure on a channel portion of a semiconductor substrate, forming an interlevel dielectric layer over the gate structure, and forming a opening through the interlevel dielectric layer to an exposed surface of the semiconductor substrate containing at least one of the source region and the drain region. A metal semiconductor alloy contact is formed on the exposed surface of the semiconductor substrate. At least one dielectric sidewall spacer is formed on sidewalls of the opening. An interconnect is formed within the opening in direct contact with the metal semiconductor alloy contact.Type: ApplicationFiled: December 7, 2010Publication date: June 7, 2012Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jian Yu, Jeffrey B. Johnson, Zhengwen Li, Chengwen Pei, Michael Hargrove
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Patent number: 8048791Abstract: Methods for forming a semiconductor device comprising a semiconductor substrate are provided. In accordance with an exemplary embodiment, a method comprises forming a channel layer overlying the semiconductor substrate, forming a channel capping layer having a first surface overlying the channel layer, oxidizing the first surface of the channel capping layer, and depositing a high-k dielectric layer overlying the channel capping layer.Type: GrantFiled: February 23, 2009Date of Patent: November 1, 2011Assignee: GLOBALFOUNDRIES Inc.Inventors: Michael Hargrove, Richard J. Carter, Ying H Tsang, George Kluth, Kisik Choi
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Publication number: 20110254092Abstract: A semiconductor is formed on an ETSOI layer, the thin Si layer of an ETSOI substrate, with enhanced channel stress. Embodiments include semiconductor devices having dual stress liners on the back surface of the ETSOI layer. An embodiment includes forming an ETSOI substrate comprising an extra thin layer of Si on a backside substrate with an insulating layer, e.g., a BOX, there between, forming a semiconductor device on the Si surface, removing the backside substrate, as by CMP and the insulting layer, as by wet etching, and forming a stress liner on the backside of the remaining Si layer opposite the semiconductor device. The use of stress liners on the backside of the ETSOI layer enhances channel stress without modifying ETSOI semiconductor process flow.Type: ApplicationFiled: April 14, 2010Publication date: October 20, 2011Applicant: GLOBALFOUNDRIES Inc.Inventors: Bin Yang, Michael Hargrove
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Patent number: 8026539Abstract: Methods are provided for forming a semiconductor device comprising a semiconductor substrate. In accordance with an exemplary embodiment, a method comprises the steps of forming a high-k dielectric layer overlying the semiconductor substrate, forming a metal-comprising gate layer overlying the high-k dielectric layer, forming a doped silicon-comprising capping layer overlying the metal-comprising gate layer, and depositing a silicon-comprising gate layer overlying the doped silicon-comprising capping layer.Type: GrantFiled: February 18, 2009Date of Patent: September 27, 2011Assignee: GLOBALFOUNDRIES Inc.Inventors: Michael Hargrove, Frank Bin Yang, Rohit Pal
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Publication number: 20110169083Abstract: A method of fabricating a semiconductor device with back side conductive plugs is provided here. The method begins by forming a gate structure overlying a semiconductor-on-insulator (SOI) substrate. The SOI substrate has a support layer, an insulating layer overlying the support layer, an active semiconductor region overlying the insulating layer, and an isolation region outboard of the active semiconductor region. A first section of the gate structure is formed overlying the isolation region and a second section of the gate structure is formed overlying the active semiconductor region. The method continues by forming source/drain regions in the active semiconductor region, and thereafter removing the support layer from the SOI substrate. Next, the method forms conductive plugs for the gate structure and the source/drain regions, where each of the conductive plugs passes through the insulating layer.Type: ApplicationFiled: January 14, 2010Publication date: July 14, 2011Applicant: GLOBALFOUNDRIES INC.Inventors: Bin YANG, Rohit PAL, Michael HARGROVE
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Publication number: 20110169084Abstract: A method of fabricating a semiconductor device with back side conductive plugs is provided here. The method begins by forming a gate structure overlying a semiconductor-on-insulator (SOI) substrate. The SOI substrate has a support layer, an insulating layer overlying the support layer, an active semiconductor region overlying the insulating layer, and an isolation region outboard of the active semiconductor region. A first section of the gate structure is formed overlying the isolation region and a second section of the gate structure is formed overlying the active semiconductor region. The method continues by forming source/drain regions in the active semiconductor region, and thereafter removing the support layer from the SOI substrate. Next, the method forms conductive plugs for the gate structure and the source/drain regions, where each of the conductive plugs passes through the insulating layer.Type: ApplicationFiled: January 14, 2010Publication date: July 14, 2011Applicant: GLOBALFOUNDRIES INC.Inventors: Bin YANG, Rohit PAL, Michael HARGROVE
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Publication number: 20110121397Abstract: Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods are provided. Methods for fabricating a semiconductor device include providing a semiconductor substrate having an active region and a shallow trench isolation (STI) region. Epitaxial layer is formed on the active region to define a lateral overhang portion in a divot at the active region/STI region interface. A gate stack is formed having a first gate stack-forming layer overlying the semiconductor substrate. First gate stack-forming layer includes a non-conformal layer of metal gate-forming material which is directionally deposited to form a thinned break portion just below the lateral overhang portion. After the step of forming the gate stack, a first portion of the non-conformal layer is in the gate stack and a second portion is exposed. The thinned break portion at least partially isolates the first and second portions during subsequent etch chemistries.Type: ApplicationFiled: February 4, 2011Publication date: May 26, 2011Applicant: GLOBALFOUNDRIES INC.Inventors: Rohit PAL, Michael HARGROVE, Frank Bin YANG
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Publication number: 20110095341Abstract: Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods are provided. Methods for fabricating a semiconductor device include providing a semiconductor substrate having an active region and a shallow trench isolation (STI) region. Epitaxial layer is formed on the active region to define a lateral overhang portion in a divot at the active region/STI region interface. A gate stack is formed having a first gate stack-forming layer overlying the semiconductor substrate. First gate stack-forming layer includes a non-conformal layer of metal gate-forming material which is directionally deposited to form a thinned break portion just below the lateral overhang portion. After the step of forming the gate stack, a first portion of the non-conformal layer is in the gate stack and a second portion is exposed. The thinned break portion at least partially isolates the first and second portions during subsequent etch chemistries.Type: ApplicationFiled: October 22, 2009Publication date: April 28, 2011Applicant: GLOBALFOUNDRIES INC.Inventors: Rohit Pal, Michael Hargrove, Frank Bin Yang
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Patent number: 7932143Abstract: Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods are provided. Methods for fabricating a semiconductor device include providing a semiconductor substrate having an active region and a shallow trench isolation (STI) region. Epitaxial layer is formed on the active region to define a lateral overhang portion in a divot at the active region/STI region interface. A gate stack is formed having a first gate stack-forming layer overlying the semiconductor substrate. First gate stack-forming layer includes a non-conformal layer of metal gate-forming material which is directionally deposited to form a thinned break portion just below the lateral overhang portion. After the step of forming the gate stack, a first portion of the non-conformal layer is in the gate stack and a second portion is exposed. The thinned break portion at least partially isolates the first and second portions during subsequent etch chemistries.Type: GrantFiled: October 22, 2009Date of Patent: April 26, 2011Assignee: GlobalFoundries Inc.Inventors: Rohit Pal, Michael Hargrove, Frank Bin Yang
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Publication number: 20100213553Abstract: Methods for forming a semiconductor device comprising a semiconductor substrate are provided. In accordance with an exemplary embodiment, a method comprises forming a channel layer overlying the semiconductor substrate, forming a channel capping layer having a first surface overlying the channel layer, oxidizing the first surface of the channel capping layer, and depositing a high-k dielectric layer overlying the channel capping layer.Type: ApplicationFiled: February 23, 2009Publication date: August 26, 2010Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Michael HARGROVE, Richard J. CARTER, Ying H. TSANG, George KLUTH, Kisik CHOI
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Publication number: 20100213555Abstract: Methods for forming a semiconductor device comprising a semiconductor substrate are provided. In accordance with an exemplary embodiment, a method comprises forming a silicon oxide layer overlying the semiconductor substrate, forming a metal oxide gate capping layer overlying the silicon oxide layer, depositing a first metal gate electrode layer overlying the metal oxide gate capping layer, and removing a portion of the first metal gate electrode layer and the metal oxide gate capping layer to form a gate stack.Type: ApplicationFiled: February 23, 2009Publication date: August 26, 2010Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Michael HARGROVE, Richard J. CARTER, Ying H. TSANG, George KLUTH, Kisik CHOI
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Publication number: 20100207176Abstract: Methods are provided for forming a semiconductor device comprising a semiconductor substrate. In accordance with an exemplary embodiment, a method comprises the steps of forming a high-k dielectric layer overlying the semiconductor substrate, forming a metal-comprising gate layer overlying the high-k dielectric layer, forming a doped silicon-comprising capping layer overlying the metal-comprising gate layer, and depositing a silicon-comprising gate layer overlying the doped silicon-comprising capping layer.Type: ApplicationFiled: February 18, 2009Publication date: August 19, 2010Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Michael Hargrove, Frank Bin Yang, Rohit Pal