Patents by Inventor Michael Hargrove
Michael Hargrove has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9472554Abstract: Integrated circuits that have a FinFET and methods of fabricating the integrated circuits are provided herein. In an embodiment, a method of fabricating an integrated circuit having a FinFET includes providing a substrate comprising fins. The fins include semiconductor material. A first metal oxide layer is formed over sidewall surfaces of the fins. The first metal oxide layer includes a first metal oxide. The first metal oxide layer is recessed to a depth below a top surface of the fins to form a recessed first metal oxide layer. The top surface and sidewall surfaces of the fins at a top portion of the fins are free from the first metal oxide layer. A gate electrode structure is formed over the top surface and sidewall surfaces of the fins at the top portion of the fins. The recessed first metal oxide layer is recessed beneath the gate electrode structure.Type: GrantFiled: July 31, 2013Date of Patent: October 18, 2016Assignee: GLOBALFOUNDRIES, INC.Inventors: Michael Hargrove, Yanxiang Liu, Christian Gruensfelder
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Patent number: 9373721Abstract: One device disclosed includes a gate structure positioned around a perimeter surface of the fin, a layer of channel semiconductor material having an axial length in the channel length direction of the device that corresponds approximately to the overall width of the gate structure being positioned between the gate structure and around the outer perimeter surface of the fin, wherein an inner surface of the layer of channel semiconductor material is spaced apart from and does not contact the outer perimeter surface of the fin. One method disclosed involves, among other things, forming first and second layers of semiconductor material around the fin, forming a gate structure around the second semiconductor material, removing the portions of the first and second layers of semiconductor material positioned laterally outside of sidewall spacers and removing the first layer of semiconductor material positioned below the second layer of semiconductor material.Type: GrantFiled: February 7, 2014Date of Patent: June 21, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Ajey Poovannummoottil Jacob, Ruilong Xie, Michael Hargrove
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Patent number: 9343300Abstract: The present disclosure is directed to forming relatively abrupt junctions between the channel region and source/drain regions of a PMOS transistor device with a germanium-containing channel region. A liner layer is formed in previously formed source/drain cavities prior to the formation of epi semiconductor material in the source/drain cavities above the liner layer. The materials for the liner layer and, particularly, the concentration of germanium (if any is present) are adjusted relative to the germanium concentration in the channel region and the epi source/drain material such that, during an anneal process, dopant materials (e.g., boron) that diffuse from the source/drain region during the anneal process tend to accumulate in or near the liner layer.Type: GrantFiled: April 15, 2015Date of Patent: May 17, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Ajey Poovannummoottil Jacob, Michael Hargrove, Jody A. Fronheiser, Murat Kerem Akarvardar
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Patent number: 9318342Abstract: One illustrative method disclosed herein includes forming a plurality of initial fins in a substrate, wherein at least one of the initial fins is a to-be-removed fin, forming a material adjacent the initial fins, forming a fin removal masking layer above the plurality of initial fins, removing a desired portion of the at least one to-be-removed fin by: (a) performing a recess etching process on the material to remove a portion, but not all, of the material positioned adjacent the sidewalls of the at least one to-be-removed fin, (b) after performing the recess etching process, performing a fin recess etching process to remove a portion, but not all, of the at least one to be removed fin and (c) repeating steps (a) and (b) until the desired amount of the at least one to-be-removed fin is removed.Type: GrantFiled: July 29, 2015Date of Patent: April 19, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Ruilong Xie, Andreas Knorr, Ajey Poovannummoottil Jacob, Michael Hargrove
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Patent number: 9312387Abstract: Disclosed are methods and devices that involve formation of alternating layers of different semiconductor materials in the channel region of FinFET devices. The methods and devices disclosed herein involve forming a doped silicon substrate fin and thereafter forming a layer of silicon/germanium around the substrate fin. The methods and devices also include forming a gate structure around the layer of silicon/germanium using gate first or gate last techniques.Type: GrantFiled: November 1, 2013Date of Patent: April 12, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Ajey Poovannummoottil Jacob, Murat Kerem Akarvardar, Michael Hargrove, Ruilong Xie
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Publication number: 20160093713Abstract: A transistor device includes a semiconductor substrate and a gate structure positioned above a surface of the semiconductor substrate. The gate structure includes a high-k gate insulation layer positioned above the surface of the semiconductor substrate and at least one work-function adjusting layer of material positioned above the high-k gate insulation layer, wherein an upper surface of the at least one work-function adjusting layer of material has a stepped profile when viewed in cross-section taken in a gate-width direction of the transistor device. The gate structure further includes a layer of conductive material positioned on the stepped upper surface of the at least one work-function adjusting layer of material.Type: ApplicationFiled: December 9, 2015Publication date: March 31, 2016Inventors: Ruilong Xie, Xiuyu Cai, Andy C. Wei, Qi Zhang, Ajey Poovannummoottil Jacob, Michael Hargrove
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Patent number: 9236258Abstract: One method disclosed herein includes forming a sacrificial gate structure comprised of upper and lower sacrificial gate electrodes, performing at least one etching process to define a patterned upper sacrificial gate electrode comprised of a plurality of trenches that expose a portion of a surface of the lower sacrificial gate electrode and performing another etching process through the patterned upper sacrificial gate electrode to remove the lower sacrificial gate electrode and a sacrificial gate insulation layer and thereby define a first portion of a replacement gate cavity that is at least partially positioned under the patterned upper sacrificial gate electrode.Type: GrantFiled: April 23, 2014Date of Patent: January 12, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Ruilong Xie, Xiuyu Cai, Andy C. Wei, Qi Zhang, Ajey Poovannummoottil Jacob, Michael Hargrove
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Publication number: 20150340238Abstract: One illustrative method disclosed herein includes forming a plurality of initial fins in a substrate, wherein at least one of the initial fins is a to-be-removed fin, forming a material adjacent the initial fins, forming a fin removal masking layer above the plurality of initial fins, removing a desired portion of the at least one to-be-removed fin by: (a) performing a recess etching process on the material to remove a portion, but not all, of the material positioned adjacent the sidewalls of the at least one to-be-removed fin, (b) after performing the recess etching process, performing a fin recess etching process to remove a portion, but not all, of the at least one to be removed fin and (c) repeating steps (a) and (b) until the desired amount of the at least one to-be-removed fin is removed.Type: ApplicationFiled: July 29, 2015Publication date: November 26, 2015Inventors: Ruilong Xie, Andreas Knorr, Ajey Poovannummoottil Jacob, Michael Hargrove
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Publication number: 20150311081Abstract: One method disclosed herein includes forming a sacrificial gate structure comprised of upper and lower sacrificial gate electrodes, performing at least one etching process to define a patterned upper sacrificial gate electrode comprised of a plurality of trenches that expose a portion of a surface of the lower sacrificial gate electrode and performing another etching process through the patterned upper sacrificial gate electrode to remove the lower sacrificial gate electrode and a sacrificial gate insulation layer and thereby define a first portion of a replacement gate cavity that is at least partially positioned under the patterned upper sacrificial gate electrode.Type: ApplicationFiled: April 23, 2014Publication date: October 29, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Ruilong Xie, Xiuyu Cai, Andy C. Wei, Qi Zhang, Ajey Poovannummoottil Jacob, Michael Hargrove
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Patent number: 9147730Abstract: One illustrative method disclosed herein includes forming a plurality of initial fins in a substrate, wherein at least one of the initial fins is a to-be-removed fin, forming a material adjacent the initial fins, forming a fin removal masking layer above the plurality of initial fins, removing a desired portion of the at least one to-be-removed fin by: (a) performing a recess etching process on the material to remove a portion, but not all, of the material positioned adjacent the sidewalls of the at least one to-be-removed fin, (b) after performing the recess etching process, performing a fin recess etching process to remove a portion, but not all, of the at least one to be removed fin and (c) repeating steps (a) and (b) until the desired amount of the at least one to-be-removed fin is removed.Type: GrantFiled: March 3, 2014Date of Patent: September 29, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Ruilong Xie, Andreas Knorr, Ajey Poovannummoottil Jacob, Michael Hargrove
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Publication number: 20150270346Abstract: Disclosed herein are various methods of forming replacement gate structures with a recessed channel region. In one example, the method includes forming a sacrificial gate structure above a semiconducting substrate, removing the sacrificial gate structure to thereby define an initial gate opening having sidewalls and to expose a surface of the substrate and performing an etching process on the exposed surface of the substrate to define a recessed channel in the substrate. The method includes the additional steps of forming a sidewall spacer within the initial gate opening on the sidewalls of the initial gate opening to thereby define a final gate opening and forming a replacement gate structure in the final gate opening.Type: ApplicationFiled: June 5, 2015Publication date: September 24, 2015Inventors: Kuldeep Amarnath, Michael Hargrove, Srikanth Samavedam
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Patent number: 9142674Abstract: Fin field-effect transistor devices and methods of forming the fin field-effect transistor devices are provided herein. In an embodiment, a fin field-effect transistor device includes a semiconductor substrate that has a fin. A gate electrode structure overlies the fin. Source and drain halo and/or extension regions and epitaxially-grown source regions and drain regions are formed in the fin and are disposed adjacent to the gate electrode structure. A body contact is disposed on a contact surface of the fin, and the body contact is spaced separately from the halo and/or extension regions and the epitaxially-grown source regions and drain regions.Type: GrantFiled: February 10, 2014Date of Patent: September 22, 2015Assignee: GLOBALFOUNDRIES, INC.Inventors: Yanxiang Liu, Michael Hargrove, Christian Gruensfelder
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Publication number: 20150255555Abstract: One illustrative method disclosed herein involves, among other things, forming a first epi semiconductor material on the exposed opposite sidewalls of a fin to thereby define a semiconductor body, performing at least one etching process to remove at least a portion of the substrate portion of the fin positioned between the first epi semiconductor materials positioned on the opposite sidewalls of the fin and to thereby define a back-gate cavity, forming a back-gate insulating material within the back-gate cavity and on the first epi semiconductor materials, forming a back-gate electrode on the back-gate insulation material within the back-gate cavity and forming a gate structure comprised of a gate insulation layer and a gate electrode around the semiconductor bodies.Type: ApplicationFiled: March 5, 2014Publication date: September 10, 2015Applicant: GLOBALFOUNDRIES INC.Inventors: Ruilong Xie, Ajey Poovannummoottil Jacob, Michael Hargrove, William J. Taylor, Jr.
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Publication number: 20150249127Abstract: One illustrative method disclosed herein includes forming a plurality of initial fins in a substrate, wherein at least one of the initial fins is a to-be-removed fin, forming a material adjacent the initial fins, forming a fin removal masking layer above the plurality of initial fins, removing a desired portion of the at least one to-be-removed fin by: (a) performing a recess etching process on the material to remove a portion, but not all, of the material positioned adjacent the sidewalls of the at least one to-be-removed fin, (b) after performing the recess etching process, performing a fin recess etching process to remove a portion, but not all, of the at least one to be removed fin and (c) repeating steps (a) and (b) until the desired amount of the at least one to-be-removed fin is removed.Type: ApplicationFiled: March 3, 2014Publication date: September 3, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Ruilong Xie, Andreas Knorr, Ajey Poovannummoottil Jacob, Michael Hargrove
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Publication number: 20150228792Abstract: One device disclosed includes a gate structure positioned around a perimeter surface of the fin, a layer of channel semiconductor material having an axial length in the channel length direction of the device that corresponds approximately to the overall width of the gate structure being positioned between the gate structure and around the outer perimeter surface of the fin, wherein an inner surface of the layer of channel semiconductor material is spaced apart from and does not contact the outer perimeter surface of the fin. One method disclosed involves, among other things, forming first and second layers of semiconductor material around the fin, forming a gate structure around the second semiconductor material, removing the portions of the first and second layers of semiconductor material positioned laterally outside of sidewall spacers and removing the first layer of semiconductor material positioned below the second layer of semiconductor material.Type: ApplicationFiled: February 7, 2014Publication date: August 13, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Ajey Poovannummoottil Jacob, Ruilong Xie, Michael Hargrove
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Patent number: 9099492Abstract: Disclosed herein are various methods of forming replacement gate structures with a recessed channel region. In one example, the method includes forming a sacrificial gate structure above a semiconducting substrate, removing the sacrificial gate structure to thereby define an initial gate opening having sidewalls and to expose a surface of the substrate and performing an etching process on the exposed surface of the substrate to define a recessed channel in the substrate. The method includes the additional steps of forming a sidewall spacer within the initial gate opening on the sidewalls of the initial gate opening to thereby define a final gate opening and forming a replacement gate structure in the final gate opening.Type: GrantFiled: March 26, 2012Date of Patent: August 4, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Kuldeep Amarnath, Michael Hargrove, Srikanth Samavedam
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Publication number: 20150123166Abstract: are methods and devices that involve formation of alternating layers of different semiconductor materials in the channel region of FinFET devices. The methods and devices disclosed herein involve forming a doped silicon substrate fin and thereafter forming a layer of silicon/germanium around the substrate fin. The methods and devices also include forming a gate structure around the layer of silicon/germanium using gate first or gate last techniques.Type: ApplicationFiled: November 1, 2013Publication date: May 7, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Ajey Poovannummoottil Jacob, Murat Kerem Akarvardar, Michael Hargrove, Ruilong Xie
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Patent number: 8987078Abstract: A method of forming a semiconductor device is provided that includes forming a gate structure on a channel portion of a semiconductor substrate, forming an interlevel dielectric layer over the gate structure, and forming a opening through the interlevel dielectric layer to an exposed surface of the semiconductor substrate containing at least one of the source region and the drain region. A metal semiconductor alloy contact is formed on the exposed surface of the semiconductor substrate. At least one dielectric sidewall spacer is formed on sidewalls of the opening. An interconnect is formed within the opening in direct contact with the metal semiconductor alloy contact.Type: GrantFiled: September 17, 2013Date of Patent: March 24, 2015Assignees: International Business Machines Corporation, GLOBAL FOUNDRIES, Inc.Inventors: Jian Yu, Jeffrey B. Johnson, Zhengwen Li, Chengwen Pei, Michael Hargrove
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Publication number: 20150034941Abstract: Integrated circuits that have a FinFET and methods of fabricating the integrated circuits are provided herein. In an embodiment, a method of fabricating an integrated circuit having a FinFET includes providing a substrate comprising fins. The fins include semiconductor material. A first metal oxide layer is formed over sidewall surfaces of the fins. The first metal oxide layer includes a first metal oxide. The first metal oxide layer is recessed to a depth below a top surface of the fins to form a recessed first metal oxide layer. The top surface and sidewall surfaces of the fins at a top portion of the fins are free from the first metal oxide layer. A gate electrode structure is formed over the top surface and sidewall surfaces of the fins at the top portion of the fins. The recessed first metal oxide layer is recessed beneath the gate electrode structure.Type: ApplicationFiled: July 31, 2013Publication date: February 5, 2015Applicant: GLOBALFOUNDRIES, Inc.Inventors: Michael HARGROVE, Yanxiang LIU, Christian GRUENSFELDER
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Publication number: 20140264633Abstract: Fin field-effect transistor devices and methods of forming the fin field-effect transistor devices are provided herein. In an embodiment, a fin field-effect transistor device includes a semiconductor substrate that has a fin. A gate electrode structure overlies the fin. Source and drain halo and/or extension regions and epitaxially-grown source regions and drain regions are formed in the fin and are disposed adjacent to the gate electrode structure. A body contact is disposed on a contact surface of the fin, and the body contact is spaced separately from the halo and/or extension regions and the epitaxially-grown source regions and drain regions.Type: ApplicationFiled: February 10, 2014Publication date: September 18, 2014Applicant: GLOBALFOUNDRIES, Inc.Inventors: Yanxiang Liu, Michael Hargrove, Christian Gruensfelder