Abstract: A method of fabricating a semiconductor transistor device is provided. The fabrication method begins by forming a gate structure overlying a layer of semiconductor material, such as silicon. Then, spacers are formed about the sidewalls of the gate structure. Next, ions of an amorphizing species are implanted into the semiconductor material at a tilted angle toward the gate structure. The gate structure and the spacers are used as an ion implantation mask during this step. The ions form amorphized regions in the semiconductor material. Thereafter, the amorphized regions are selectively removed, resulting in corresponding recesses in the semiconductor material. In addition, the recesses are filled with stress inducing semiconductor material, and fabrication of the semiconductor transistor device is completed.

Abstract: A method of fabricating a semiconductor transistor device is provided. The fabrication method begins by forming a gate structure overlying a layer of semiconductor material, such as silicon. Then, spacers are formed about the sidewalls of the gate structure. Next, ions of an amorphizing species are implanted into the semiconductor material at a tilted angle toward the gate structure. The gate structure and the spacers are used as an ion implantation mask during this step. The ions form amorphized regions in the semiconductor material. Thereafter, the amorphized regions are selectively removed, resulting in corresponding recesses in the semiconductor material. In addition, the recesses are filled with stress inducing semiconductor material, and fabrication of the semiconductor transistor device is completed.

Abstract: An integrated variable inductor is achieved by placing a second closed-loop inductor immediately above or below a primary inductor. The closed-loop configuration of the second inductor may be broken on-chip by several ways, including use of a transistor to selectively short together both ends of the second inductor. If one wishes to alter the inherent inductance characteristics of the primary inductor, the transistor coupling both ends of the second inductor is actuated. Thus, a current applied to the primary inductor induces a current in the second inductor by inductive coupling. The second current in the second inductor then alters the impedance of the primary inductor by mutual inductance. Thus, the inductance value of the primary inductor is altered. To remove the influence of the second inductor on the primary inductor, the closed-loop configuration of the second inductor is broken.

Abstract: MOS transistors having high-k spacers and methods for fabricating such transistors are provided. One exemplary method comprises forming a gate stack overlying a semiconductor substrate and forming an offset spacer about sidewalls of the gate stack. The offset spacer is formed of a high-k dielectric material that results in a low interface trap density between the offset spacer and the semiconductor substrate. First ions of a conductivity-determining impurity type are implanted into the semiconductor substrate using the gate stack and the offset spacer as an implantation mask to form spaced-apart impurity-doped extensions.

Abstract: The construction of Shallow Trench Isolation, STI, regions is integrated in to a SIMOX fabrication process for a Silicon On Insulator, SOI, wafer. Prior to the beginning of the SOI process, a preferred nitrogen (N2) implant is applied to the silicon wafer in areas designated as active regions. The nitrogen modifies the oxidation rate of later implanted oxygen. Regions where the N2 is implanted result in thinner oxide layers. The SIMOX process can begin following the implantation of nitrogen. This results in buried regions of thick and thin oxide layers at fixed depths in the Si substrate. Excess Si on top of the buried thick and thin oxide regions can be polished down to the thick oxide regions to form the active device regions over the thin oxide regions. Thus, the SOI wafer exhibits an STI structure upon completion of the SOI process without a need for additional STI manufacturing steps.

Abstract: The capacitive loading effects of an ESD circuit having an electrostatic-protection diode are reduced by using a capacitance compensation circuit. Under normal operation when no electrostatic discharge is experienced, the capacitance reduction circuit maintains a reverse bias across the electrostatic-protection diode, which causes the diode's capacitance to be reduced below a predetermined value. When an electrostatic discharged is experienced, the capacitance compensation circuit removes the applied reverse bias, and shunts the electrostatic-protection diode to a power rail.

Abstract: An improved integrated LC resonator and methods for making and using the same are disclosed. The resonator includes (i) a first capacitor plate; (ii) an inductor over and in electrical communication with the first capacitor plate; and (iii) a second capacitor plate over and in electrical communication with the inductor. The method of making includes sequentially forming a first capacitor plate, a first dielectric layer thereon, a first via and an inductor, a second dielectric layer on the inductor, and a second via and a second capacitor plate. Each of the capacitor plates and the inductor are generally formed in different integrated circuit layers (for example, different metallization layers). Embodiments of the present invention can advantageously provide an integrated LC resonator tank having: (i) relatively high Q by reducing or minimizing parasitic effects; and (ii) relatively high shielding from the semiconductor substrate.

Abstract: A method for maintaining signal integrity of a differential output signal generated from a differential driver is disclosed. The method includes receiving the differential output signal from the differential driver. Once received, the method includes tuning the differential output signal by exposing the differential output signal to an inductance. The inductance is configured to reduce signal mismatch between complementary signals of the differential output signal. The signal mismatch is a result of having each of the complementary signals exposed to different capacitive loading. A device and system is also provided, which include integrating an inductor between the output leads of a differential driver. The inductor is sized for the particular frequency of operation, and the inductor provides an inductance that assists in eliminating mismatch between the complementary signals of the differential output.

Abstract: A universal, substrate Padset for de-embedding pad and signal line parasitics has an input pad group including a first input signal pad and a first ground pad; an output pad group including a first output signal pad and a second ground pad; a first input-signal-routing network for routing the first input signal pad to a first input node of a first predetermined test device; a first output-signal-routing network for routing the first output signal pad to a first output node of the first predetermined test device; a second input-signal-routing network for routing the first input signal pad to a second input node of a second predetermined test device; and a second output-signal-routing network for routing the first output signal pad to a second output node of the second predetermined test device. The layout configuration of the first test device is different from the layout configuration of the second test device.

Abstract: An improved integrated LC resonator and methods for making and using the same are disclosed. The resonator includes (i) a first capacitor plate; (ii) an inductor over and in electrical communication with the first capacitor plate; and (iii) a second capacitor plate over and in electrical communication with the inductor. The method of making includes sequentially forming a first capacitor plate, a first dielectric layer thereon, a first via and an inductor, a second dielectric layer on the inductor, and a second via and a second capacitor plate. Each of the capacitor plates and the inductor are generally formed in different integrated circuit layers (for example, different metallization layers). Embodiments of the present invention can advantageously provide an integrated LC resonator tank having: (i) relatively high Q by reducing or minimizing parasitic effects; and (ii) relatively high shielding from the semiconductor substrate.

Abstract: An integrated variable inductor is achieved by placing a second closed-loop inductor immediately above or below a primary inductor. The closed-loop configuration of the second inductor may be broken on-chip by several ways, including use of a transistor to selectively short together both ends of the second inductor. If one wishes to alter the inherent inductance characteristics of the primary inductor, the transistor coupling both ends of the second inductor is actuated. Thus, a current applied to the primary inductor induces a current in the second inductor by inductive coupling. The second current in the second inductor then alters the impedance of the primary inductor by mutual inductance. Thus, the inductance value of the primary inductor is altered. To remove the influence of the second inductor on the primary inductor, the closed-loop configuration of the second inductor is broken.

Abstract: The construction of Shallow Trench Isolation, STI, regions is integrated in to a SIMOX fabrication process for a Silicon On Insulator, SOI, wafer. Prior to the beginning of the SOI process, a preferred nitrogen (N2) implant is applied to the silicon wafer in areas designated as active regions. The nitrogen modifies the oxidation rate of later implanted oxygen. Regions where the N2 is implanted result in thinner oxide layers. The SIMOX process can begin following the implantation of nitrogen. This results in buried regions of thick and thin oxide layers at fixed depths in the Si substrate. Excess Si on top of the buried thick and thin oxide regions can be polished down to the thick oxide regions to form the active device regions over the thin oxide regions. Thus, the SOI wafer exhibits an STI structure upon completion of the SOI process without a need for additional STI manufacturing steps.

Abstract: A method for maintaining signal integrity of a differential output signal generated from a differential driver is disclosed. The method includes receiving the differential output signal from the differential driver. Once received, the method includes tuning the differential output signal by exposing the differential output signal to an inductance. The inductance is configured to reduce signal mismatch between complementary signals of the differential output signal. The signal mismatch is a result of having each of the complementary signals exposed to different capacitive loading. A device and system is also provided, which include integrating an inductor between the output leads of a differential driver. The inductor is sized for the particular frequency of operation, and the inductor provides an inductance that assists in eliminating mismatch between the complementary signals of the differential output.

Abstract: A structure, and a method for fabricating the structure, for the isolation of electronic devices is disclosed. The electronic devices are processed in substrates comprising a SiGe based layer underneath a strained Si layer. The isolation structure comprises a trench extending downward from the substrate top surface and penetrating into the SiGe based layer, forming a sidewall in the substrate. An epitaxial Si liner is selectively deposited onto the trench sidewall, and subsequently thermally oxidized. The trench is filled with a trench dielectric, which protrudes above the substrate top surface.

Abstract: The capacitive loading effects of an ESD circuit having an electrostatic-protection diode are reduced by using a capacitance compensation circuit. Under normal operation when no electrostatic discharge is experienced, the capacitance reduction circuit maintains a reverse bias across the electrostatic-protection diode, which causes the diode's capacitance to be reduced below a predetermined value. When an electrostatic discharged is experienced, the capacitance compensation circuit removes the applied reverse bias, and shunts the electrostatic-protection diode to a power rail.

Abstract: A failure response method is provided. The method includes preparing a bridge having an address of a telecommunication system for common access by a predetermined group of resources, sending an alpha communication communicating the telecommunication system address to the predetermined group of resources, coordinating the resources through the bridge to correct the failure, and sending a final message to the predetermined group of resources by the telecommunication system when the failure has been corrected. A failure response system is also provided. The failure response system includes a storage device containing contact data for a predetermined group of resources to be utilized when responding to a failure and an address of a telecommunication system for common access by the predetermined group of resources.