Patents by Inventor Michael Hutzler

Michael Hutzler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240128329
    Abstract: In an embodiment, a semiconductor device is provided that includes a semiconductor substrate having a first major surface, one or more trenches formed in the first major surface and having a base and a side wall extending from the base to the first major surface, an anchoring layer, and a conductive member arranged in the one or more trenches and spaced apart from the side wall of the one or more trenches by a cavity formed in the one or more trenches . The anchoring layer extends from the first major surface of the semiconductor substrate over the cavity and onto an upper surface of the conductive member.
    Type: Application
    Filed: October 3, 2023
    Publication date: April 18, 2024
    Inventors: Michael Hutzler, Alexander Breymesser, Laszlo Juhasz
  • Publication number: 20240065006
    Abstract: In an embodiment, a transistor device includes: a support layer having a first major surface and a second major surface opposing the first major surface; a source contact arranged on the first major surface of the support layer; a drain contact arranged on the second major surface of the support layer; and a gate electrode arranged in a first trench formed in the first major surface of the support layer. The first trench has a base and a side wall extending from the base to the first major surface. The drain contact is arranged under the base of the first trench. A region with gate-controlled conductivity is formed between the source contact and the drain contact. The region with gate-controlled conductivity is formed in an organic semiconductor layer.
    Type: Application
    Filed: October 16, 2023
    Publication date: February 22, 2024
    Inventor: Michael Hutzler
  • Publication number: 20230246071
    Abstract: The application relates to a semiconductor transistor device, having a source region, a body region including a channel region extending in a vertical direction, a drain region, a gate region arranged aside the channel region in a lateral direction, and a body contact region made of an electrically conductive material, wherein the body contact region forms a body contact area, the body contact region being in an electrical contact with the body region via the body contact area, and wherein the body contact area is tilted with respect to the vertical direction and the lateral direction.
    Type: Application
    Filed: April 5, 2023
    Publication date: August 3, 2023
    Inventors: Li Juin Yip, Oliver Blank, Heimo Hofer, Michael Hutzler, Thomas Ralf Siemieniec
  • Patent number: 11682703
    Abstract: A method of producing a semiconductor device includes: forming, in a semiconductor substrate, a drift region of a first conductivity type, a body region of a second conductivity type above the drift region, and a source region of the first conductivity type separated from the drift region by the body region; forming rows of spicular-shaped field plate structures in the semiconductor substrate, the spicular-shaped field plate structures extending through the source region and the body region into the drift region; forming stripe-shaped gate structures in the semiconductor substrate and separating adjacent rows of the spicular-shaped field plate structures; and forming a current spread region of the first conductivity type below the body region in semiconductor mesas between adjacent ones of the spicular-shaped field plate structures and which are devoid of the stripe-shaped gate structures, the current spread region configured to increase channel current distribution in the semiconductor mesas.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: June 20, 2023
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Siemieniec, Michael Hutzler
  • Publication number: 20230178647
    Abstract: In an embodiment, a transistor device a semiconductor substrate having a main surface, and a cell field including a plurality of transistor cells of a power transistor. The cell field further includes: a body region of a second conductivity type; a source region of a first conductivity type on or in the body region, the first conductivity type opposing the second conductivity type; a gate trench in the main surface of the semiconductor substrate; a gate dielectric lining the gate trench; a metal gate electrode arranged in the gate trench on the gate dielectric; and an electrically insulating cap arranged on the metal gate electrode. A method of fabricating a gate of the transistor device is also described.
    Type: Application
    Filed: January 30, 2023
    Publication date: June 8, 2023
    Inventors: Ingmar Neumann, Michael Hutzler, David Laforet, Roland Moennich, Thomas Ralf Siemieniec
  • Patent number: 11670684
    Abstract: The application relates to a semiconductor transistor device, having a source region, a body region including a channel region extending in a vertical direction, a drain region, a gate region arranged aside the channel region in a lateral direction, and a body contact region made of an electrically conductive material, wherein the body contact region forms a body contact area, the body contact region being in an electrical contact with the body region via the body contact area, and wherein the body contact area is tilted with respect to the vertical direction and the lateral direction.
    Type: Grant
    Filed: February 1, 2021
    Date of Patent: June 6, 2023
    Assignee: Infineon Technologies Austria AG
    Inventors: Li Juin Yip, Oliver Blank, Heimo Hofer, Michael Hutzler, Ralf Siemieniec
  • Patent number: 11600723
    Abstract: In an embodiment, a transistor device includes a semiconductor substrate having a main surface, a cell field including a plurality of transistor cells, and an edge termination region laterally surrounding the cell field. The cell field includes a gate trench in the main surface of the semiconductor substrate, a gate dielectric lining the gate trench, a metal gate electrode arranged in the gate trench on the gate dielectric, and an electrically insulating cap arranged on the metal gate electrode and within the gate trench.
    Type: Grant
    Filed: February 1, 2021
    Date of Patent: March 7, 2023
    Assignee: Infineon Technologies Austria AG
    Inventors: Ingmar Neumann, Michael Hutzler, David Laforet, Roland Moennich, Ralf Siemieniec
  • Publication number: 20220376062
    Abstract: A semiconductor device includes a transistor cell region, and a first termination region devoid of transistor cells. The transistor cell region includes a gate structure, a plurality of needle-shaped first field plate structures, body regions of a second conductivity type, and source regions of a first conductivity type. The first termination region surrounds the transistor cell region and includes needle-shaped second field plate structures. The needle-shaped first field plate structures are arranged in a first pattern and the needle-shaped second field plate structures are arranged in a second pattern.
    Type: Application
    Filed: August 5, 2022
    Publication date: November 24, 2022
    Inventors: Ralf Siemieniec, Oliver Blank, Franz Hirler, Michael Hutzler, David Laforet, Cédric Ouvrard, Li Juin Yip
  • Patent number: 11462620
    Abstract: A semiconductor device includes a semiconductor substrate, a transistor cell region formed in the semiconductor substrate and an inner termination region formed in the semiconductor substrate and devoid of transistor cells. The transistor cell region includes a gate structure extending from a first surface into the semiconductor substrate, a plurality of needle-shaped first field plate structures extending from the first surface into the semiconductor substrate, body regions of a second conductivity type, and source regions of a first conductivity type formed between the body regions and the first surface. The inner termination region surrounds the transistor cell region and includes needle-shaped second field plate structures extending from the first surface into the semiconductor substrate. The needle-shaped first field plate structures are arranged in a first pattern and the needle-shaped second field plate structures are arranged in a second pattern.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: October 4, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Siemieniec, Oliver Blank, Franz Hirler, Michael Hutzler, David Laforet, Cédric Ouvrard, Li Juin Yip
  • Patent number: 11296218
    Abstract: A semiconductor device includes a semiconductor body having first and second opposing surfaces, an active area including active transistor cells, and an edge termination region laterally surrounding the active area. Each active transistor cell includes a mesa and a columnar trench having a field plate. The edge termination region includes inactive cells each including a columnar termination trench having a field plate, and a termination mesa including a drift region of a first conductivity type. The edge termination region includes a transition region laterally surrounding the active region and an outer termination region laterally surrounding the transition region. In the transition region, the termination mesa includes a body region of a second conductivity type arranged on the drift region. In the outer termination region, the drift region extends to the first surface. A buried doped region of the edge termination region is positioned in the transition and outer termination regions.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: April 5, 2022
    Assignees: Infineon Technologies Austria AG, Infineon Technologies Americas Corp.
    Inventors: Ralf Siemieniec, Adam Amali, Michael Hutzler, Laszlo Juhasz, David Laforet, Cedric Ouvrard, Li Juin Yip
  • Patent number: 11195713
    Abstract: In one aspect, a method of forming a silicon-insulator layer is provided. The method includes arranging a silicon structure in a plasma etch process chamber and applying a plasma to the silicon structure in the plasma etch process chamber at a temperature of the silicon structure equal to or below 100° C. The plasma includes a component and a halogen derivate, thereby forming the silicon-insulator layer. The silicon-insulator layer includes silicon and the component. In another aspect, a semiconductor device is provided having a silicon-insulator layer formed by the method.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: December 7, 2021
    Assignee: Infineon Technologies AG
    Inventors: Joachim Hirschler, Georg Ehrentraut, Christoffer Erbert, Klaus Goeschl, Markus Heinrici, Michael Hutzler, Wolfgang Koell, Stefan Krivec, Ingmar Neumann, Mathias Plappert, Michael Roesner, Olaf Storbeck
  • Publication number: 20210249534
    Abstract: In an embodiment, a transistor device includes a semiconductor substrate having a main surface, a cell field including a plurality of transistor cells, and an edge termination region laterally surrounding the cell field. The cell field includes a gate trench in the main surface of the semiconductor substrate, a gate dielectric lining the gate trench, a metal gate electrode arranged in the gate trench on the gate dielectric, and an electrically insulating cap arranged on the metal gate electrode and within the gate trench.
    Type: Application
    Filed: February 1, 2021
    Publication date: August 12, 2021
    Inventors: Ingmar Neumann, Michael Hutzler, David Laforet, Roland Moennich, Ralf Siemieniec
  • Publication number: 20210249510
    Abstract: The application relates to a semiconductor transistor device, having a source region, a body region including a channel region extending in a vertical direction, a drain region, a gate region arranged aside the channel region in a lateral direction, and a body contact region made of an electrically conductive material, wherein the body contact region forms a body contact area, the body contact region being in an electrical contact with the body region via the body contact area, and wherein the body contact area is tilted with respect to the vertical direction and the lateral direction.
    Type: Application
    Filed: February 1, 2021
    Publication date: August 12, 2021
    Inventors: Li Juin Yip, Oliver Blank, Heimo Hofer, Michael Hutzler, Ralf Siemieniec
  • Publication number: 20210234010
    Abstract: A method of producing a semiconductor device includes: forming, in a semiconductor substrate, a drift region of a first conductivity type, a body region of a second conductivity type above the drift region, and a source region of the first conductivity type separated from the drift region by the body region; forming rows of spicular-shaped field plate structures in the semiconductor substrate, the spicular-shaped field plate structures extending through the source region and the body region into the drift region; forming stripe-shaped gate structures in the semiconductor substrate and separating adjacent rows of the spicular-shaped field plate structures; and forming a current spread region of the first conductivity type below the body region in semiconductor mesas between adjacent ones of the spicular-shaped field plate structures and which are devoid of the stripe-shaped gate structures, the current spread region configured to increase channel current distribution in the semiconductor mesas.
    Type: Application
    Filed: April 13, 2021
    Publication date: July 29, 2021
    Inventors: Ralf Siemieniec, Michael Hutzler
  • Patent number: 11004945
    Abstract: A semiconductor device includes: a semiconductor substrate having a drift region of a first conductivity type, a body region of a second conductivity type formed above the drift region, and a source region of the first conductivity type separated from the drift region by the body region; rows of spicular-shaped field plate structures formed in the semiconductor substrate, the spicular-shaped field plate structures extending through the source region and the body region into the drift region; stripe-shaped gate structures formed in the semiconductor substrate and separating adjacent rows of the spicular-shaped field plate structures; and a current spread region of the first conductivity type formed below the body region in semiconductor mesas between adjacent ones of the spicular-shaped field plate structures and which are devoid of the stripe-shaped gate structures. The current spread region is configured to increase channel current distribution in the semiconductor mesas.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: May 11, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Siemieniec, Michael Hutzler
  • Publication number: 20210066459
    Abstract: A semiconductor device includes a semiconductor substrate, a transistor cell region formed in the semiconductor substrate and an inner termination region formed in the semiconductor substrate and devoid of transistor cells. The transistor cell region includes a gate structure extending from a first surface into the semiconductor substrate, a plurality of needle-shaped first field plate structures extending from the first surface into the semiconductor substrate, body regions of a second conductivity type, and source regions of a first conductivity type formed between the body regions and the first surface. The inner termination region surrounds the transistor cell region and includes needle-shaped second field plate structures extending from the first surface into the semiconductor substrate. The needle-shaped first field plate structures are arranged in a first pattern and the needle-shaped second field plate structures are arranged in a second pattern.
    Type: Application
    Filed: November 16, 2020
    Publication date: March 4, 2021
    Inventors: Ralf Siemieniec, Oliver Blank, Franz Hirler, Michael Hutzler, David Laforet, Cédric Ouvrard, Li Juin Yip
  • Patent number: 10872957
    Abstract: A semiconductor device includes a semiconductor substrate, a transistor cell region formed in the semiconductor substrate and an inner termination region formed in the semiconductor substrate and devoid of transistor cells. The transistor cell region includes a plurality of transistor cells and a gate structure that forms a grid separating transistor sections of the transistor cells from each other, each of the transistor sections including a needle-shaped first field plate structure extending from a first surface into the semiconductor substrate. The inner termination region surrounds the transistor cell region and includes needle-shaped second field plate structures extending from the first surface into the semiconductor substrate. The first field plate structures form a first portion of a regular pattern and the second field plate structures form a second portion of the same regular pattern.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: December 22, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Siemieniec, Oliver Blank, Franz Hirler, Michael Hutzler, David Laforet, Cedric Ouvrard, Li Juin Yip
  • Patent number: 10868173
    Abstract: A semiconductor device includes a semiconductor substrate having drift and body regions. The drift region includes upper and lower drift regions. An active area includes a plurality of spicular trenches extending through the body region and into the drift region. Each spicular trench in the active area has a lower end which together define a lower end of the upper drift region extending towards a first side and a lower drift region extending from the lower end of the upper drift region towards a second side. The edge termination area includes spicular termination trenches extending at least into the upper drift region. A surface doping region arranged in the upper drift region in the edge termination area extends to the first side, is spaced apart from the lower end of the upper drift region, and has a net doping concentration lower than that of the upper drift region.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: December 15, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Cedric Ouvrard, Adam Amali, Oliver Blank, Michael Hutzler, David Laforet, Harsh Naik, Ralf Siemieniec, Li Juin Yip
  • Patent number: 10868170
    Abstract: A power semiconductor die conducts a load current between front and back side load terminals. The die includes an active region with a plurality of columnar trench cells. Each columnar trench cell includes: a section of a drift zone, a section of a channel zone and a section of a source zone, the channel zone section being electrically connected to the front side load terminal and isolating the source zone section from the drift zone section; and a control section with at least one control electrode in a control trench. An edge termination region between the die edge and the active region includes a front side zone configured to have an electrical potential different from an electrical potential of the front side load terminal. An isolating trench structure is arranged between the front side zone and the channel zone which is electrically connected to the front side load terminal.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: December 15, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Michael Hutzler, Christof Altstaetter
  • Publication number: 20200373396
    Abstract: A semiconductor device includes: a semiconductor substrate having a drift region of a first conductivity type, a body region of a second conductivity type formed above the drift region, and a source region of the first conductivity type separated from the drift region by the body region; rows of spicular-shaped field plate structures formed in the semiconductor substrate, the spicular-shaped field plate structures extending through the source region and the body region into the drift region; stripe-shaped gate structures formed in the semiconductor substrate and separating adjacent rows of the spicular-shaped field plate structures; and a current spread region of the first conductivity type formed below the body region in semiconductor mesas between adjacent ones of the spicular-shaped field plate structures and which are devoid of the stripe-shaped gate structures. The current spread region is configured to increase channel current distribution in the semiconductor mesas.
    Type: Application
    Filed: May 21, 2019
    Publication date: November 26, 2020
    Inventors: Ralf Siemieniec, Michael Hutzler