Patents by Inventor Michael Hutzler

Michael Hutzler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10868173
    Abstract: A semiconductor device includes a semiconductor substrate having drift and body regions. The drift region includes upper and lower drift regions. An active area includes a plurality of spicular trenches extending through the body region and into the drift region. Each spicular trench in the active area has a lower end which together define a lower end of the upper drift region extending towards a first side and a lower drift region extending from the lower end of the upper drift region towards a second side. The edge termination area includes spicular termination trenches extending at least into the upper drift region. A surface doping region arranged in the upper drift region in the edge termination area extends to the first side, is spaced apart from the lower end of the upper drift region, and has a net doping concentration lower than that of the upper drift region.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: December 15, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Cedric Ouvrard, Adam Amali, Oliver Blank, Michael Hutzler, David Laforet, Harsh Naik, Ralf Siemieniec, Li Juin Yip
  • Patent number: 10868170
    Abstract: A power semiconductor die conducts a load current between front and back side load terminals. The die includes an active region with a plurality of columnar trench cells. Each columnar trench cell includes: a section of a drift zone, a section of a channel zone and a section of a source zone, the channel zone section being electrically connected to the front side load terminal and isolating the source zone section from the drift zone section; and a control section with at least one control electrode in a control trench. An edge termination region between the die edge and the active region includes a front side zone configured to have an electrical potential different from an electrical potential of the front side load terminal. An isolating trench structure is arranged between the front side zone and the channel zone which is electrically connected to the front side load terminal.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: December 15, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Michael Hutzler, Christof Altstaetter
  • Publication number: 20200373396
    Abstract: A semiconductor device includes: a semiconductor substrate having a drift region of a first conductivity type, a body region of a second conductivity type formed above the drift region, and a source region of the first conductivity type separated from the drift region by the body region; rows of spicular-shaped field plate structures formed in the semiconductor substrate, the spicular-shaped field plate structures extending through the source region and the body region into the drift region; stripe-shaped gate structures formed in the semiconductor substrate and separating adjacent rows of the spicular-shaped field plate structures; and a current spread region of the first conductivity type formed below the body region in semiconductor mesas between adjacent ones of the spicular-shaped field plate structures and which are devoid of the stripe-shaped gate structures. The current spread region is configured to increase channel current distribution in the semiconductor mesas.
    Type: Application
    Filed: May 21, 2019
    Publication date: November 26, 2020
    Inventors: Ralf Siemieniec, Michael Hutzler
  • Publication number: 20200365724
    Abstract: A semiconductor device includes a semiconductor body having first and second opposing surfaces, an active area including active transistor cells, and an edge termination region laterally surrounding the active area. Each active transistor cell includes a mesa and a columnar trench having a field plate. The edge termination region includes inactive cells each including a columnar termination trench having a field plate, and a termination mesa including a drift region of a first conductivity type. The edge termination region includes a transition region laterally surrounding the active region and an outer termination region laterally surrounding the transition region. In the transition region, the termination mesa includes a body region of a second conductivity type arranged on the drift region. In the outer termination region, the drift region extends to the first surface. A buried doped region of the edge termination region is positioned in the transition and outer termination regions.
    Type: Application
    Filed: May 13, 2020
    Publication date: November 19, 2020
    Inventors: Ralf Siemieniec, Adam Amali, Michael Hutzler, Laszlo Juhasz, David Laforet, Cedric Ouvrard, Li Juin Yip
  • Publication number: 20200328303
    Abstract: A semiconductor device includes a semiconductor substrate having drift and body regions. The drift region includes upper and lower drift regions. An active area includes a plurality of spicular trenches extending through the body region and into the drift region. Each spicular trench in the active area has a lower end which together define a lower end of the upper drift region extending towards a first side and a lower drift region extending from the lower end of the upper drift region towards a second side. The edge termination area includes spicular termination trenches extending at least into the upper drift region. A surface doping region arranged in the upper drift region in the edge termination area extends to the first side, is spaced apart from the lower end of the upper drift region, and has a net doping concentration lower than that of the upper drift region.
    Type: Application
    Filed: June 25, 2020
    Publication date: October 15, 2020
    Inventors: Cedric Ouvrard, Adam Amali, Oliver Blank, Michael Hutzler, David Laforet, Harsh Naik, Ralf Siemieniec, Li Juin Yip
  • Patent number: 10727331
    Abstract: A semiconductor device includes a semiconductor substrate having drift and body regions. The drift region includes upper and lower drift regions. An active area includes a plurality of spicular trenches extending through the body region and into the drift region. Each spicular trench in the active area has a lower end which together define a lower end of the upper drift region extending towards a first side and a lower drift region extending from the lower end of the upper drift region towards a second side. The edge termination area includes spicular termination trenches extending at least into the upper drift region. A surface doping region arranged in the upper drift region in the edge termination area extends to the first side, is spaced apart from the lower end of the upper drift region, and has a net doping concentration lower than that of the upper drift region.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: July 28, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Cedric Ouvrard, Adam Amali, Oliver Blank, Michael Hutzler, David Laforet, Harsh Naik, Ralf Siemieniec, Li Juin Yip
  • Patent number: 10700172
    Abstract: In an embodiment, a semiconductor device is provided that includes a semiconductor body having a first conductivity type, a first major surface and a second major surface opposite the first major surface, a gate arranged on the first major surface, a body region having a second conductivity type opposite the first conductivity type, the body region extending into the semiconductor body from the first major surface, a source region having the first conductivity type, the source region being arranged in the body region, a buried channel shielding region having the second conductivity type, a contact region having the second conductivity type, and a field plate arranged in a trench extending into the semiconductor body from the first major surface.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: June 30, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Michael Hutzler, Franz Hirler, Ralf Siemieniec
  • Publication number: 20200127102
    Abstract: A semiconductor device includes a semiconductor substrate, a transistor cell region formed in the semiconductor substrate and an inner termination region formed in the semiconductor substrate and devoid of transistor cells. The transistor cell region includes a plurality of transistor cells and a gate structure that forms a grid separating transistor sections of the transistor cells from each other, each of the transistor sections including a needle-shaped first field plate structure extending from a first surface into the semiconductor substrate. The inner termination region surrounds the transistor cell region and includes needle-shaped second field plate structures extending from the first surface into the semiconductor substrate. The first field plate structures form a first portion of a regular pattern and the second field plate structures form a second portion of the same regular pattern.
    Type: Application
    Filed: November 22, 2019
    Publication date: April 23, 2020
    Inventors: Ralf Siemieniec, Oliver Blank, Franz Hirler, Michael Hutzler, David Laforet, Cedric Ouvrard, Li Juin Yip
  • Patent number: 10529811
    Abstract: According to an embodiment of a power semiconductor device, the device includes a semiconductor body coupled to a first load terminal and a second load terminal and configured to conduct a load current between the first load terminal and the second load terminal. A trench extends into the semiconductor body along an extension direction and includes an insulator. A first electrode structure included in the trench is configured to control the load current. A second electrode structure included in the trench is arranged separately and electrically insulated from the first electrode structure. The first electrode structure and the second electrode structure are spatially displaced from each other along the extension direction such that they do not have a common extension range along the extension direction. Each of the first electrode structure and the second electrode structure is made of a metal.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: January 7, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Thomas Feil, Michael Hutzler
  • Publication number: 20190385842
    Abstract: In one aspect, a method of forming a silicon-insulator layer is provided. The method includes arranging a silicon structure in a plasma etch process chamber and applying a plasma to the silicon structure in the plasma etch process chamber at a temperature of the silicon structure equal to or below 100° C. The plasma includes a component and a halogen derivate, thereby forming the silicon-insulator layer. The silicon-insulator layer includes silicon and the component. In another aspect, a semiconductor device is provided having a silicon-insulator layer formed by the method.
    Type: Application
    Filed: May 30, 2019
    Publication date: December 19, 2019
    Inventors: Joachim Hirschler, Georg Ehrentraut, Christoffer Erbert, Klaus Goeschl, Markus Heinrici, Michael Hutzler, Wolfgang Koell, Stefan Krivec, Ingmar Neumann, Mathias Plappert, Michael Roesner, Olaf Storbeck
  • Patent number: 10510846
    Abstract: A semiconductor device includes a semiconductor substrate, a transistor cell region formed in the semiconductor substrate and an inner termination region formed in the semiconductor substrate and devoid of transistor cells. The transistor cell region includes a plurality of transistor cells and a gate structure that forms a grid separating transistor sections of the transistor cells from each other, each of the transistor sections including a needle-shaped first field plate structure extending from a first surface into the semiconductor substrate. The inner termination region surrounds the transistor cell region and includes needle-shaped second field plate structures extending from the first surface into the semiconductor substrate. The first field plate structures form a first portion of a regular pattern and the second field plate structures form a second portion of the same regular pattern.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: December 17, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Siemieniec, Oliver Blank, Franz Hirler, Michael Hutzler, David Laforet, Cedric Ouvrard, Li Juin Yip
  • Patent number: 10453929
    Abstract: A method of manufacturing a power metal oxide semiconductor field effect transistor includes: forming a field electrode in a field plate trench in a main surface of a semiconductor substrate; forming a gate trench in the main surface, the gate trench extending in a first direction parallel to the main surface; and for a gate electrode in the gate trench, the gate electrode being made of a gate electrode material that comprises a metal. The field plate trench is formed to have an extension length in the first direction which is less than double of an extension length of the field plate trench in a second direction, the second direction being perpendicular to the first direction.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: October 22, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: David Laforet, Oliver Blank, Michael Hutzler, Cedric Ouvrard, Ralf Siemieniec, Li Juin Yip
  • Patent number: 10403728
    Abstract: A semiconductor device includes needle-shaped trenches in a semiconductor substrate, each of which includes a field electrode electrically insulated from the semiconductor substrate. Source doping regions and body doping regions of a transistor arrangement are formed in the semiconductor substrate between neighboring ones of the needle-shaped trenches. Gate trenches extend through the source doping regions and the body doping regions. The device further includes a first insulation layer above the semiconductor substrate, an etch stop layer on the first insulation layer, a second insulation layer on the etch stop layer, and an electrically conductive material on the second insulation layer and which contacts the field electrodes, source doping regions and body doping regions through openings which extend through the second insulation layer, etch stop layer and first insulation layer.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: September 3, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Michael Hutzler, Christoph Gruber
  • Publication number: 20190172916
    Abstract: According to an embodiment of a power semiconductor device, the device includes a semiconductor body coupled to a first load terminal and a second load terminal and configured to conduct a load current between the first load terminal and the second load terminal. A trench extends into the semiconductor body along an extension direction and includes an insulator. A first electrode structure included in the trench is configured to control the load current. A second electrode structure included in the trench is arranged separately and electrically insulated from the first electrode structure. The first electrode structure and the second electrode structure are spatially displaced from each other along the extension direction such that they do not have a common extension range along the extension direction. Each of the first electrode structure and the second electrode structure is made of a metal.
    Type: Application
    Filed: January 18, 2019
    Publication date: June 6, 2019
    Inventors: Thomas Feil, Michael Hutzler
  • Publication number: 20190165160
    Abstract: A power semiconductor die conducts a load current between front and back side load terminals. The die includes an active region with a plurality of columnar trench cells. Each columnar trench cell includes: a section of a drift zone, a section of a channel zone and a section of a source zone, the channel zone section being electrically connected to the front side load terminal and isolating the source zone section from the drift zone section; and a control section with at least one control electrode in a control trench. An edge termination region between the die edge and the active region includes a front side zone configured to have an electrical potential different from an electrical potential of the front side load terminal. An isolating trench structure is arranged between the front side zone and the channel zone which is electrically connected to the front side load terminal.
    Type: Application
    Filed: November 28, 2018
    Publication date: May 30, 2019
    Inventors: Michael Hutzler, Christof Altstaetter
  • Publication number: 20190140059
    Abstract: A semiconductor device includes needle-shaped trenches in a semiconductor substrate, each of which includes a field electrode electrically insulated from the semiconductor substrate. Source doping regions and body doping regions of a transistor arrangement are formed in the semiconductor substrate between neighboring ones of the needle-shaped trenches. Gate trenches extend through the source doping regions and the body doping regions. The device further includes a first insulation layer above the semiconductor substrate, an etch stop layer on the first insulation layer, a second insulation layer on the etch stop layer, and an electrically conductive material on the second insulation layer and which contacts the field electrodes, source doping regions and body doping regions through openings which extend through the second insulation layer, etch stop layer and first insulation layer.
    Type: Application
    Filed: December 28, 2018
    Publication date: May 9, 2019
    Inventors: Michael Hutzler, Christoph Gruber
  • Publication number: 20190123153
    Abstract: In an embodiment, a semiconductor device is provided that includes a semiconductor body having a first conductivity type, a first major surface and a second major surface opposite the first major surface, a gate arranged on the first major surface, a body region having a second conductivity type opposite the first conductivity type, the body region extending into the semiconductor body from the first major surface, a source region having the first conductivity type, the source region being arranged in the body region, a buried channel shielding region having the second conductivity type, a contact region having the second conductivity type, and a field plate arranged in a trench extending into the semiconductor body from the first major surface.
    Type: Application
    Filed: October 18, 2018
    Publication date: April 25, 2019
    Inventors: Michael Hutzler, Franz Hirler, Ralf Siemieniec
  • Patent number: 10236351
    Abstract: A method of processing a power semiconductor device includes: providing a semiconductor body with a trench extending into the semiconductor body along an extension direction and including an insulator; providing a monolithic electrode zone within the trench; and removing a section of the monolithic electrode zone within the trench to divide the monolithic electrode zone into at least a first electrode structure and a second electrode structure arranged separately and electrically insulated from each other.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: March 19, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Thomas Feil, Michael Hutzler
  • Patent number: 10199468
    Abstract: A method for forming a semiconductor device includes forming a first insulation layer on a semiconductor substrate and forming a structured etch stop layer. Further, the method includes depositing a second insulation layer after forming the structured etch stop layer and forming a structured mask layer on the second insulation layer. Additionally, the method includes etching portions of the second insulation layer uncovered by the structured mask layer and portions of the first insulation layer uncovered by the structured etch stop layer to uncover at least one of a portion of the semiconductor substrate and an electrode located within a trench. Further, the method includes depositing electrically conductive material to form an electrical contact to at least one of the uncovered electrode and the uncovered portion of the semiconductor substrate.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: February 5, 2019
    Assignee: Infineon Technologies Austra AG
    Inventors: Michael Hutzler, Christoph Gruber
  • Publication number: 20190006513
    Abstract: A semiconductor device includes a semiconductor substrate having drift and body regions. The drift region includes upper and lower drift regions. An active area includes a plurality of spicular trenches extending through the body region and into the drift region. Each spicular trench in the active area has a lower end which together define a lower end of the upper drift region extending towards a first side and a lower drift region extending from the lower end of the upper drift region towards a second side. The edge termination area includes spicular termination trenches extending at least into the upper drift region. A surface doping region arranged in the upper drift region in the edge termination area extends to the first side, is spaced apart from the lower end of the upper drift region, and has a net doping concentration lower than that of the upper drift region.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 3, 2019
    Inventors: Cedric Ouvrard, Adam Amali, Oliver Blank, Michael Hutzler, David Laforet, Harsh Naik, Ralf Siemieniec, Li Juin Yip