Abstract: A semiconductor device includes a first and second pin, a first lead finger coupled to the first pin and a second lead finger coupled to the second pin, and a die coupled to the lead fingers. The die includes a first die pad coupled to the first lead finger and a second die pad coupled to the second lead finger. The die further includes a first output driver coupled to the first die pad and a second output driver coupled to the second die pad. The first output driver is coupled to the first die pad via an extended metal trace. The extended metal trace compensates for differences in electrical length between the first lead finger and the second lead finger.

Abstract: A CMOS microprocessor chip includes an on-chip single-poly EPROM that is process compatible with the CMOS process used to manufacture the microprocessor. The EPROM is used to store manufacturing and contract related data such as serial number, customer, and process related data such as wafer number test results, binning data, etc. This provides important information for quality and reliability control. The EPROM is also used to control selection of optional microprocessor features such as speed governing, pin-out and I/O bus interface configuration. A third use is for trimming of critical circuit elements and for cache redundancy fault control.

Abstract: A receiver circuit is provided. The receiver circuit includes a differential stage that has a first input that receives a first signal, a second input that receives a reference signal and an output. The receiver circuit further includes first and second switch devices that receive the first signal and in response to this signal, couple the differential stage to a first and a second, respectively, voltages when the first signal is within a first voltage range. The receiver circuit also includes a keeper circuit that has an input that receives the first signal and an output coupled to the output of the differential stage. The keeper circuit clamps the output to a third voltage when the first signal is within a second voltage range. The keeper circuit also clamps the output to a fourth voltage when the first signal is within a third voltage range.

Abstract: An apparatus is disclosed for providing a reduced-capacitance transistor with ESD protection that can be fabricated using standard processes. The transistor includes a substrate, a source region formed in the substrate, and a well region also formed in the substrate. The transistor further includes a drain region having a first end region, a second end region, and a resistive region positioned between the first and second end regions. The drain region is formed at least partially in the well region. A drain contract is form on the first end region of the drain region. Additionally, a gate structure is included. The gate structure is formed on the substrate between the source region and the second end region of the drain region. The gate structure defines a channel region that couples the source to the drain region.

Abstract: A CMOS microprocessor chip includes an on-chip single-poly EPROM that is process-compatible with the CMOS process used to manufacture the microprocessor. The EPROM is used to store manufacturing and contract related data such as serial number, customer, and process related data such as wafer number test results, binning data, etc. This provides important information for quality and reliability control. The EPROM is also used to control selection of optional microprocessor features such as speed governing, pin-out and I/O bus interface configuration. A third use is for trimming of critical circuit elements and for cache redundancy fault control.

Abstract: A rivet system (10) locks separate parts (12, 14) of an assembly (13) together on a support fixture (20) with the clamping devices (28); which prevents release of the parts (12, 14) from the fixture (20) until a required number of rivets (51) have been counted. A rivet setting tool (50) provides insertion of the rivets (51) between the parts (12, 14), and which disposes spent rivet mandrels (62) through a vacuum tube (58) to be sensed and counted. A controller (100) automatically locks the parts in the support fixture and counts the sensed mandrels (62) to allow release of the assembly (13) only upon a predetermined count of mandrels (62).

Abstract: An input structure transmits legacy signals to internal logic of a low voltage integrated circuit. The input structure includes a first node coupled to both a resistor voltage divider and a capacitor voltage divider, both of which have center taps coupled together, and also to the internal logic. The capacitor and resistor voltage dividers function to divide the higher voltage logic level range associated with the legacy signals to the low voltage logic level range suitable for input to the internal logic.

Abstract: A low power termination method and apparatus. The termination circuit is typically coupled to a bus through an interface node to receive a rising edge of an input voltage signal. A clamping device is coupled to the interface node and coupled to receive a clamping voltage, the clamping voltage being less than a termination voltage. The termination circuit also includes a bias supply providing a bias voltage. A control terminal of the clamping device is coupled receive the bias voltage, and clamps the interface node when the input voltage signal exceeds a termination voltage. A bias excursion of the bias voltage may be provided responsive to the rising edge so that the clamping device clamps the interface node before the input voltage signal exceeds the termination voltage. Similarly, a second clamping device biased by a second bias supply may be used. The second clamping device clamps the interface node after the input voltage signal falls below an expected low voltage.

Abstract: Instrumentation and techniques to image small objects, such as but not limited to individual human chromosomes, with nanometer resolution, to cut-off identified parts of such objects, to move around and manipulate such cut-off parts on the substrate on which they are being imaged to predetermined locations on the substrate, and to remove the cut-off parts from the substrate. This is accomplished using an atomic force microscope (AFM) and by modification of the conventional cantilever stylus assembly of an AFM, such that plural cantilevers are used with either sharp-tips or knife-edges thereon. In addition, the invention can be utilized for measuring hardness of materials.

Abstract: Apparatus (10) for applying hot cushion gum (E) in a strip (12) of predetermined thickness and width to the crown surface (14) of a tire carcass (16) having a sagittal plane (68). The apparatus (10) includes a motor (M) for rotating the tire carcass (16), and extrusion means (18) for dispensing hot cushion gum through a die means (26). The angular disposition of the die means (26) may be selected relative to the sagittal plane (68) of the tire carcass (16) to determine the effective width of the strip (12) applied to the crown surface (14), rotational control mechanism (64) is also provided selectively to control the angular velocity of the rotating tire carcass (16) which determines the thickness of the strip (12). According to the present method a tire carcass (16) is mounted for rotation. The die head (26) is positionable at a selected angle (.beta.) within its angular range (.alpha.) measured transversely of the sagittal plane ( 68) of the tire carcass (16) to establish a selected, effective width (W.sub.

Abstract: An integrated circuit which includes a pair of serially arranged P channel transistor devices connected with their source and drain terminals in series. The devices are constructed as N well devices in a P substrate. Using a pair of N well devices allows higher voltages to be divided and applied across the two devices without reaching the breakdown limits of either the oxide or the junctions between different portions of the devices used in the process. These devices have been found capable of transferring ten or more volts to circuitry for programming or erasing flash EEPROM cells even the they are a part of integrated circuitry designed for only 3.3 volt usage.

Abstract: An integrated circuit which includes a pair of serially arranged P channel transistor devices connected with their source and drain terminals in series. The devices are constructed as N well devices in a P substrate. Using a pair of N well devices allows higher voltages to be divided and applied across the two devices without reaching the breakdown limits of either the oxide or the junctions between different portions of the devices used in the process. These devices have been found capable of transferring ten or more volts to circuitry for programming or erasing flash EEPROM cells even the they are a part of integrated circuitry designed for only 3.3 volt usage.

Abstract: A plurality of programmable circuits joining input terminals to output terminals in a product term of a programmable logic circuit. Each circuit includes a first multiplexor joining an input terminal to a first node, a second multiplexor joining an output terminal to the first node, and a source of signals of a first value. Further included is a first apparatus for selecting whether to transfer signals either from the first and second multiplexors or from the source of signals of the first value to the first node, and a second apparatus for selecting whether to transfer signals either from the first multiplexor or the second multiplexor to the first node A third apparatus determines whether a third multiplexor selects either the signal at the first node for transfer to the output terminal or the inverse of the signal at the first node for transfer to the output terminal.

Abstract: An integrated circuit charge pump which includes a pair of serially arranged P channel transistor devices connected with their source and drain terminals in series. The devices are constructed as N well devices in a P substrate. Using a pair of N well devices allows higher voltages to be divided and applied across the two devices without reaching the breakdown limits of either the oxide or the junctions between different portions of the devices used in the process. One of the devices has its body well connected to its drain terminal to provide a diode between the source and body well which allows the device to turn on and off when subject to a series of input pulses at its drain terminal. A third similarly biased N well P channel device is connected in series with the pair of P channel devices to provide the voltage pumping effect at an output terminal.

Abstract: Apparatus (10) for applying hot cushion gum (E) in a strip (12) of predetermined thickness and width to the crown surface (14) of a tire carcass (16) having a sagittal plane (68). The apparatus (10) includes a motor (M) for rotating the tire carcass (16), and extrusion means (18) for dispensing hot cushion gum through a die means (26). The angular disposition of the die means (26) may be selected relative to the sagittal plane (68) of the tire carcass (16) to determine the effective width of the strip (12) applied to the crown surface (14). rotational control mechanism (64) is also provided selectively to control the angular velocity of the rotating tire carcass (16) which determines the thickness of the strip (12). According to the present method a tire carcass (16) is mounted for rotation. The die head (26) is positionable at a selected angle (.beta.) within its angular range (.alpha.) measured transversely of the sagittal plane ( 68) of the tire carcass (16) to establish a selected, effective width (W.sub.

Abstract: The present invention discloses a semiconductor output circuit with temperature compensated noise control. The output circuit of the present invention presents an increase in speed, a reduction in power consumption, and a reduction in noise level as compared with the prior art temperature compensated noise control output circuits. These advantages are obtained by utilizing the present invention's current control means which current control means is driven by a temperature compensation circuit.

Abstract: An apparatus and method of increasing the speed of an input receiver circuit directly interfaces the wordlines of a memory array. The speed of the input receiver and wordline driver circuit is improved by means of an inverter and a look-ahead n-channel transistor coupled to the basic wordline driver buffer.

Abstract: The instant invention encompasses the combination of a modified electric guitar component coupled with a plurality of equivalent one-coil and equivalent two-coil transducer cradle components attached thereto upon which cradles, transducers are permanently mounted respectively. The transducer cradle components are readily amenable to detachment from and reattachment to the body of the electric guitar component and as well to speedy frontwise insertion into or frontwise removal from the modification of the electric guitar component, to wit, appropriately contoured openings in the front of the body of the electric guitar component below the level of intact guitar strings. Metallic contact rods on each cradle component receive transducer wiring emanating from a permanently mounted transducer and contact, upon insertion of a given cradle into a given opening, by way of contact points in the front wall of the opening, the internal wiring within the modified electric guitar component and ultimately, an amplifier.

Abstract: A programmable logic device is described. The programmable logic device includes a plurality of memory cells, each having a drain, a source, a floating gate, and a control gate. A first bit line is coupled the drain of each of the plurality memory cells. The bit line provides a voltage level. A second bit line is coupled to the source of each of the plurality of memory cells. The programmable logic device further includes means for controlling the voltage level to swing between a first voltage state and a second voltage state. The controlling means receives current from the first bit line to clamp the voltage level to the first voltage state when the voltage level exceeds the first voltage state. The controlling means provides current to the first bit line and limits current flow of the first bit line to maintain the voltage level to the second voltage state when the voltage level exceeds below the second voltage state.

Abstract: The present invention discloses an improved two-stage macrocell for Programmable Logic Devices. According to the first stage of the improved circuit of the present invention's macrocell, combined NOR'ing, inverting, MUX'ing, and latching functions are performed by the single first stage. This single stage replaces the prior art multiple stages for performing the same NOR'ing, inverting, MUX'ing, and latching functions of the present invention. Since the present invention replaces the prior art multiple stages with a single stage, the speed of the present invention in performing the above NOR'ing, inverting, MUX'ing, and latching functions is significantly improved over the prior art. Furthermore, the present invention also discloses a second stage for a low-noise temperature-compensated output circuit.