Patents by Inventor Michael J. Seddon

Michael J. Seddon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12132008
    Abstract: Implementations of a semiconductor device may include a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. The first largest planar surface, the second largest planar surface, and the thickness may be formed by at least two semiconductor die. The warpage of one of the first largest planar surface or the second largest planar surface may be less than 200 microns.
    Type: Grant
    Filed: July 19, 2022
    Date of Patent: October 29, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. Seddon, Francis J. Carney
  • Patent number: 12132005
    Abstract: Implementations of a semiconductor substrate may include a wafer including a first side and a second side; and a support structure coupled to the wafer at a desired location on the first side, the second side, or both the first side and the second side. The support structure may include an organic compound.
    Type: Grant
    Filed: November 13, 2023
    Date of Patent: October 29, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. Seddon, Francis J. Carney
  • Patent number: 12119294
    Abstract: A through-substrate via structure includes a conductive via structure including trench portions at a first major surface of a substrate and extending to a first distance. A first insulating structure is over sidewalls of the trench portions, and a conductive material is over the first insulating structure. A recessed region extends from a second major surface of the substrate to a second distance greater than the first distance and laterally overlaps and interfaces both trench portions. A second insulating structure includes a first portion within the recessed region and a second portion adjacent to the second major surface outside of the recessed region, which includes an outer surface overlapping the second major surface outside of the recessed region. A first conductive region includes a proximate end coupled to the conductive material through openings in the first portion, and an opposite distal that is outward from the second portion.
    Type: Grant
    Filed: March 3, 2023
    Date of Patent: October 15, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. Seddon, Francis J. Carney
  • Publication number: 20240332025
    Abstract: Various implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; applying a permanent coating material into the plurality of notches; forming a first organic material over the first side of the semiconductor substrate and the plurality of notches; thinning a second side of the semiconductor substrate opposite the first side one of to or into the plurality of notches; and singulating the semiconductor substrate through the permanent coating material into a plurality of semiconductor packages.
    Type: Application
    Filed: June 13, 2024
    Publication date: October 3, 2024
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Francis J. CARNEY, Yusheng LIN, Michael J. SEDDON, Chee Hiong CHEW, Soon Wei WANG, Eiji KUROSE
  • Patent number: 12094750
    Abstract: Implementations of a method of increasing the adhesion of a tape. Implementations may include: mounting a tape to a frame, mounting a substrate to the tape, heating the tape after mounting the substrate at one or more temperatures for a predetermined period of time, and increasing an adhesion of the tape to the substrate through heating the tape.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: September 17, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. Seddon
  • Publication number: 20240297065
    Abstract: Implementations of a curved die system may include a semiconductor die; and a die curvature support structure including an organic material coupled to a surface of the semiconductor die. The die curvature support structure may induce warpage greater than 200 microns in the surface of the semiconductor die. The die curvature support structure may be configured to induce warpage prior to coupling the semiconductor die to a correspondingly curved substrate.
    Type: Application
    Filed: May 10, 2024
    Publication date: September 5, 2024
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. SEDDON, Francis J. CARNEY
  • Publication number: 20240297106
    Abstract: A through-substrate via structure includes a conductive via structure including trench portions at a first major surface of a substrate and extending to a first distance. A first insulating structure is over sidewalls of the trench portions, and a conductive material is over the first insulating structure. A recessed region extends from a second major surface of the substrate to a second distance greater than the first distance and laterally overlaps and interfaces both trench portions. A second insulating structure includes a first portion within the recessed region and a second portion adjacent to the second major surface outside of the recessed region, which includes an outer surface overlapping the second major surface outside of the recessed region. A first conductive region includes a proximate end coupled to the conductive material through openings in the first portion, and an opposite distal that is outward from the second portion.
    Type: Application
    Filed: March 3, 2023
    Publication date: September 5, 2024
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. SEDDON, Francis J. CARNEY
  • Publication number: 20240243013
    Abstract: Implementations of a semiconductor substrate singulation process may include applying a fluid jet to a material of a die street of a plurality of die streets included in a semiconductor substrate where the semiconductor substrate may include: a plurality of die separated by the plurality of die streets; and a plurality of die support structures coupled thereto; and singulating the plurality of die and the plurality of die support structures at the plurality of die streets using the fluid jet. The fluid jet may be moved only along a length of the die street.
    Type: Application
    Filed: March 31, 2024
    Publication date: July 18, 2024
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. SEDDON
  • Patent number: 12040295
    Abstract: Implementations of semiconductor devices may include a die having a first side and a second side, a contact pad coupled to the first side of the die, and a metal layer coupled to the second side of the die. A thickness of the die may be no more than four times a thickness of the metal layer.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: July 16, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. Seddon, Takashi Noma, Kazuo Okada, Hideaki Yoshimi, Naoyuki Yomoda, Yusheng Lin
  • Patent number: 12040192
    Abstract: Various implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; applying a permanent coating material into the plurality of notches; forming a first organic material over the first side of the semiconductor substrate and the plurality of notches; thinning a second side of the semiconductor substrate opposite the first side one of to or into the plurality of notches; and singulating the semiconductor substrate through the permanent coating material into a plurality of semiconductor packages.
    Type: Grant
    Filed: July 19, 2022
    Date of Patent: July 16, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Francis J. Carney, Yusheng Lin, Michael J. Seddon, Chee Hiong Chew, Soon Wei Wang, Eiji Kurose
  • Patent number: 12020972
    Abstract: Implementations of a curved die system may include a semiconductor die; and a die curvature support structure including an organic material coupled to a surface of the semiconductor die. The die curvature support structure may induce warpage greater than 200 microns in the surface of the semiconductor die. The die curvature support structure may be configured to induce warpage prior to coupling the semiconductor die to a correspondingly curved substrate.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: June 25, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. Seddon, Francis J. Carney
  • Publication number: 20240203864
    Abstract: Implementations of a silicon-on-insulator (SOI) die may include a silicon layer including a first side and a second side, and an insulative layer coupled directly to the second side of the silicon layer. The insulative layer may not be coupled to any other silicon layer.
    Type: Application
    Filed: February 29, 2024
    Publication date: June 20, 2024
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Mark GRISWOLD, Michael J. SEDDON
  • Publication number: 20240203744
    Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; forming an organic material over the first side of the semiconductor substrate and into the plurality of notches; forming a cavity into each of a plurality of semiconductor die included in the semiconductor substrate; applying a backmetal into the cavity in each of the plurality of semiconductor die included in the semiconductor substrate; and singulating the semiconductor substrate through the organic material into a plurality of semiconductor packages.
    Type: Application
    Filed: January 18, 2024
    Publication date: June 20, 2024
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. SEDDON, Francis J. CARNEY, Chee Hiong CHEW, Soon Wei WANG, Eiji KUROSE
  • Publication number: 20240186182
    Abstract: Implementations of methods of singulating a plurality of die included in a substrate may include forming a plurality of die on a first side of a substrate, forming a backside metal layer on a second side of a substrate, applying a photoresist layer over the backside metal layer, patterning the photoresist layer along a die street of the substrate, and etching through the backside metal layer located in the die street of the substrate. The substrate may be exposed through the etch. The method may also include singulating the plurality of die included in the substrate through removing a substrate material in the die street.
    Type: Application
    Filed: February 16, 2024
    Publication date: June 6, 2024
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. SEDDON
  • Publication number: 20240178060
    Abstract: Implementations of die singulation systems and related methods may include forming a plurality of die on a first side of a substrate, forming a seed layer on a second side of a substrate opposite the first side of the substrate, using a shadow mask, applying a mask layer over the seed layer, forming a backside metal layer over the seed layer, removing the mask layer, and singulating the plurality of die included in the substrate through removing substrate material in the die street and through removing seed layer material in the die street.
    Type: Application
    Filed: February 6, 2024
    Publication date: May 30, 2024
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. SEDDON
  • Patent number: 11987874
    Abstract: Implementations of methods of forming a metal layer on a semiconductor wafer may include: placing a semiconductor wafer into an evaporator dome and adding a material to a crucible located a predetermined distance from the semiconductor wafer. The semiconductor wafer may include an average thickness of less than 39 microns. The method may also include heating the material in the crucible to a vapor and depositing the material on a second side of the semiconductor wafer.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: May 21, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. Seddon
  • Publication number: 20240145266
    Abstract: Implementations of a packaging system may include a wafer; and a curvature adjustment structure coupled thereto where the curvature adjustment structure may be configured to alter a curvature of a largest planar surface of the wafer.
    Type: Application
    Filed: December 28, 2023
    Publication date: May 2, 2024
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. SEDDON, Francis J. CARNEY
  • Patent number: 11972980
    Abstract: Implementations of a semiconductor substrate singulation process may include applying a fluid jet to a material of a die street of a plurality of die streets included in a semiconductor substrate where the semiconductor substrate may include: a plurality of die separated by the plurality of die streets; and a plurality of die support structures coupled thereto; and singulating the plurality of die and the plurality of die support structures at the plurality of die streets using the fluid jet. The fluid jet may be moved only along a length of the die street.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: April 30, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. Seddon
  • Patent number: 11948880
    Abstract: Implementations of a silicon-on-insulator (SOI) die may include a silicon layer including a first side and a second side, and an insulative layer coupled directly to the second side of the silicon layer. The insulative layer may not be coupled to any other silicon layer.
    Type: Grant
    Filed: October 4, 2022
    Date of Patent: April 2, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Mark Griswold, Michael J. Seddon
  • Patent number: 11942366
    Abstract: Implementations of die singulation systems and related methods may include forming a plurality of die on a first side of a substrate, forming a seed layer on a second side of a substrate opposite the first side of the substrate, using a shadow mask, applying a mask layer over the seed layer, forming a backside metal layer over the seed layer, removing the mask layer, and singulating the plurality of die included in the substrate through removing substrate material in the die street and through removing seed layer material in the die street.
    Type: Grant
    Filed: October 3, 2022
    Date of Patent: March 26, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. Seddon