Patents by Inventor Michael J. Seddon

Michael J. Seddon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11342189
    Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; forming an organic material over the first side of the semiconductor substrate and into the plurality of notches; forming a cavity into each of a plurality of semiconductor die included in the semiconductor substrate; applying a backmetal into the cavity in each of the plurality of semiconductor die included in the semiconductor substrate; and singulating the semiconductor substrate through the organic material into a plurality of semiconductor packages.
    Type: Grant
    Filed: August 5, 2020
    Date of Patent: May 24, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. Seddon, Francis J. Carney, Chee Hiong Chew, Soon Wei Wang, Eiji Kurose
  • Patent number: 11289358
    Abstract: Implementations of systems for thinning a semiconductor substrate may include: a substrate chuck configured to receive a semiconductor substrate for thinning, a spindle, a grinding wheel coupled to the spindle, and a water medium configured to be in contact with the semiconductor substrate during thinning. An ultrasonic energy source may be directly coupled to the substrate chuck, the spindle, the grinding wheel, the water medium, or any combination thereof.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: March 29, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. Seddon
  • Patent number: 11289381
    Abstract: Implementations of a method for aligning a semiconductor wafer for singulation may include: providing a semiconductor wafer having a first side and a second side. The first side of the wafer may include a plurality of die and the plurality of die may be separated by streets. The semiconductor wafer may include an edge ring around a perimeter of the wafer on the second side of the wafer. The wafer may also include a metal layer on the second side of the wafer. The metal layer may substantially cover the edge ring. The method may include grinding the edge ring to create an edge exclusion area and aligning the semiconductor wafer with a saw using a camera positioned in the edge exclusion area on the second side of the wafer. Aligning the wafer may include using three or more alignment features included in the edge exclusion area.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: March 29, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. Seddon, Takashi Noma
  • Patent number: 11289380
    Abstract: Implementations of methods of singulating a plurality of die comprised in a substrate may include forming a plurality of die on a first side of a substrate, forming a backside metal layer on a second side of a substrate, applying a polymer layer over the backside metal layer and forming a groove entirely through the polymer layer and partially through a thickness of the backside metal layer. The groove may be located in a die street of the substrate. The method may also include etching through a remaining portion of the backside metal layer located in the die street, removing the polymer layer, singulating the plurality of die in the substrate by removing substrate material in the die street.
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: March 29, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. Seddon
  • Publication number: 20220084895
    Abstract: Implementations of methods of making a semiconductor device may include: providing a partial semiconductor wafer. The method may also include providing a wafer holder including a tape portion with one or more openings through the tape portion. The method may include mounting the partial semiconductor wafer over the one or more openings in the tape portion of the wafer holder and providing an electrical connection to the partial semiconductor wafer through the one or more openings in the tape portion during probe test.
    Type: Application
    Filed: December 1, 2021
    Publication date: March 17, 2022
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. SEDDON
  • Patent number: 11254565
    Abstract: Implementations of absolute pressure sensor devices may include a microelectromechanical system (MEMS) absolute pressure sensor coupled over a controller die. The MEMS absolute pressure sensor may be mechanically coupled to the controller die and may also be configured to electrically couple with the controller die. A perimeter of the controller die may be one of the same size and larger than a perimeter of the MEMS absolute pressure sensor. The controller die may be configured to electrically couple with a module through an electrical connector.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: February 22, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. Seddon
  • Patent number: 11257724
    Abstract: Implementations of methods of making a semiconductor device may include: providing a partial semiconductor wafer. The method may also include providing a wafer holder including a tape portion with one or more openings through the tape portion. The method may include mounting the partial semiconductor wafer over the one or more openings in the tape portion of the wafer holder and providing an electrical connection to the partial semiconductor wafer through the one or more openings in the tape portion during probe test.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: February 22, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. Seddon
  • Publication number: 20220028812
    Abstract: A semiconductor wafer has an edge support ring around a perimeter of the semiconductor wafer and conductive layer formed over a surface of the semiconductor wafer within the edge support ring. A first stencil is disposed over the edge support ring with first openings aligned with the conductive layer. The first stencil includes a horizontal portion over the edge support ring, and a step-down portion extending the first openings to the conductive layer formed over the surface of the semiconductor wafer. The horizontal portion may have a notch with the edge support ring disposed within the notch. A plurality of bumps is dispersed over the first stencil to occupy the first openings over the conductive layer. A second stencil is disposed over the edge support ring with second openings aligned with the conductive layer to deposit a flux material in the second openings over the conductive layer.
    Type: Application
    Filed: October 5, 2021
    Publication date: January 27, 2022
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. SEDDON, Takashi NOMA, Kazuhiro SAITO
  • Patent number: 11222840
    Abstract: Implementations of a silicon-on-insulator (SOI) die may include a silicon layer including a first side and a second side, and an insulative layer coupled directly to the second side of the silicon layer. The insulative layer may not be coupled to any other silicon layer.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: January 11, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Mark Griswold, Michael J. Seddon
  • Patent number: 11211359
    Abstract: A semiconductor device has a plurality of interconnected modular units to form a 3D semiconductor package. Each modular unit is implemented as a vertical component or a horizontal component. The modular units are interconnected through a vertical conduction path and lateral conduction path within the vertical component or horizontal component. The vertical component and horizontal component each have an interconnect interposer or semiconductor die. A first conductive via is formed vertically through the interconnect interposer. A second conductive via is formed laterally through the interconnect interposer. The interconnect interposer can be programmable. A plurality of protrusions and recesses are formed on the vertical component or horizontal component, and a plurality of recesses on the vertical component or horizontal component. The protrusions are inserted into the recesses to interlock the vertical component and horizontal component.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: December 28, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Francis J. Carney, Michael J. Seddon
  • Publication number: 20210384077
    Abstract: Implementations of methods of singulating a plurality of die included in a substrate may include forming a groove through a backside metal layer through laser ablating a backside metal layer at a die street of a substrate and singulating a plurality of die included in the substrate through removing substrate material of the substrate in the die street.
    Type: Application
    Filed: August 23, 2021
    Publication date: December 9, 2021
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. SEDDON
  • Publication number: 20210375679
    Abstract: Implementations of a method of forming a plurality of semiconductor devices on a semiconductor substrate may include: providing a semiconductor substrate having a first surface, a second surface, a size, and a thickness where the second surface opposes the first surface and the thickness is between the first surface and the second surface. The method may include processing the semiconductor substrate through a plurality of semiconductor device fabrication processes to form a plurality of semiconductor devices on the first surface. The thickness may be between 100 microns and 575 microns and the size may be 150 mm. The semiconductor substrate may not be coupled with a carrier or support.
    Type: Application
    Filed: August 12, 2021
    Publication date: December 2, 2021
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. SEDDON
  • Publication number: 20210343540
    Abstract: Implementations of a semiconductor substrate may include a plurality of die including at least one contact; and a plurality of portions of an encapsulant on a surface of the semiconductor substrate, wherein each portion of the plurality of portions extends immediately above a plane of the at least one contact.
    Type: Application
    Filed: April 29, 2020
    Publication date: November 4, 2021
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Francis J. CARNEY, Michael J. SEDDON
  • Publication number: 20210343655
    Abstract: Implementations of a semiconductor substrate may include a wafer including a first side and a second side; and a support structure coupled to the wafer at a desired location on the first side, the second side, or both the first side and the second side. The support structure may include an organic compound.
    Type: Application
    Filed: April 29, 2020
    Publication date: November 4, 2021
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. SEDDON, Francis J. CARNEY
  • Publication number: 20210343615
    Abstract: Implementations of a semiconductor package may include a singulated die and a passivating material of a predetermined thickness across a majority of a singulated surface of the singulated die on at least one singulated surface of the singulated die.
    Type: Application
    Filed: April 29, 2020
    Publication date: November 4, 2021
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Francis J. CARNEY, Michael J. SEDDON
  • Publication number: 20210343574
    Abstract: Implementations of a curved die system may include a semiconductor die; and a die curvature support structure including an organic material coupled to a surface of the semiconductor die. The die curvature support structure may induce warpage greater than 200 microns in the surface of the semiconductor die. The die curvature support structure may be configured to induce warpage prior to coupling the semiconductor die to a correspondingly curved substrate.
    Type: Application
    Filed: April 29, 2020
    Publication date: November 4, 2021
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. SEDDON, Francis J. CARNEY
  • Publication number: 20210343604
    Abstract: Implementations of a method for healing a crack in a semiconductor substrate may include identifying a crack in a semiconductor substrate and heating an area of the semiconductor substrate including the crack until the crack is healed.
    Type: Application
    Filed: July 12, 2021
    Publication date: November 4, 2021
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. SEDDON
  • Publication number: 20210343568
    Abstract: Implementations of a semiconductor device may include a semiconductor die comprising a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and a temporary die support structure coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. The thickness may be between 0.1 microns and 125 microns. The warpage of the semiconductor die may be less than 200 microns.
    Type: Application
    Filed: April 29, 2020
    Publication date: November 4, 2021
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Francis J. CARNEY, Michael J. SEDDON
  • Publication number: 20210343608
    Abstract: Implementations of a substrate carrier may include: a top ring configured to enclose an edge of a first side of a substrate; and a bottom support configured to enclose an entire second side and an edge of the second side of the substrate.
    Type: Application
    Filed: July 12, 2021
    Publication date: November 4, 2021
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. Seddon
  • Publication number: 20210343657
    Abstract: Implementations of a semiconductor device may include a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. The first largest planar surface, the second largest planar surface, and the thickness may be formed by at least two semiconductor die. The warpage of one of the first largest planar surface or the second largest planar surface may be less than 200 microns.
    Type: Application
    Filed: April 29, 2020
    Publication date: November 4, 2021
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. SEDDON, Francis J. CARNEY