Patents by Inventor Michael L. Chabinyc
Michael L. Chabinyc has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7504331Abstract: A method of forming a self-assembled interconnect structure is described. In the method, a contact pad surface and particles in a solution are brought together. The particles are selected such that they the particles adhere to the contact pad surface. Formation of a contact is completed by pressing an opposite contact into the particles such that an electrical connection is formed via the particles between the opposite contact pad and the substrate surface contact pad. The described self-assembled interconnect structure is particularly useful in display device fabrication.Type: GrantFiled: July 27, 2005Date of Patent: March 17, 2009Assignee: Palo Alto Research Center IncorporatedInventors: David K. Fork, Thomas Hantschel, Michael L. Chabinyc
-
Patent number: 7425734Abstract: An improved transistor array for a display or sensor device is described. The display or sensor device includes a plurality of pixels. Each pixel includes a width and a length. Each pixel is addressed by a transistor. The transistor addressing each pixel has a channel with a channel width. Each channel width is greater than the width or length of the pixel being addressed. By fabricating transistors with extremely long channel widths, lower mobility semiconductor materials can easily be used to fabricate the display device.Type: GrantFiled: July 25, 2005Date of Patent: September 16, 2008Assignee: Palo Alto Research Center IncorporatedInventors: William S. Wong, Jeng Ping Lu, Alberto Salleo, Michael L. Chabinyc, Raj B. Apte, Robert A. Street
-
Patent number: 7405424Abstract: An electronic device and a method of fabricating the electronic device includes forming a first electrical contact, a dielectric layer and a second electrical contact wherein the dielectric layer is located between the first and the second electrical contacts, forming an electrically insulating layer over the dielectric layer and the first electrical contact, exposing the first and second electrical contact, the dielectric layer and a first portion of the electrically insulating layer to radiation from the side of the first electrical contact, removing a second portion of the electrically insulating layer that was not irradiated by the radiation, providing a semiconductor material over a portion of the dielectric layer, and forming at least a third electrical contact over at least a portion of the electrically insulting layer and the semiconductor material.Type: GrantFiled: March 4, 2005Date of Patent: July 29, 2008Assignee: Palo Alto Research Center IncorporatedInventors: Michael L. Chabinyc, Alberto Salleo, William S. Wong
-
Publication number: 20080152872Abstract: A method of depositing elongated nanostructures that allows accurate positioning and orientation is described. The method involves printing or otherwise depositing elongated nanostructures in a carrier solution. The deposited droplets are also elongated, usually by patterning the surface upon which the droplets are deposited. As the droplet evaporates, the fluid flow within the droplets is controlled such that the nanostructures are deposited either at the edge of the elongated droplet or the center of the elongated droplet. The described deposition technique has particular application in forming the active region of a transistor.Type: ApplicationFiled: December 22, 2006Publication date: June 26, 2008Inventors: Michael L. Chabinyc, William S. Wong
-
Publication number: 20080149920Abstract: A method of depositing elongated nanostructures that allows accurate positioning and orientation is described. The method involves printing or otherwise depositing elongated nanostructures in a carrier solution. The deposited droplets are also elongated, usually by patterning the surface upon which the droplets are deposited. As the droplet evaporates, the fluid flow within the droplets is controlled such that the nanostructures are deposited either at the edge of the elongated droplet or the center of the elongated droplet. The described deposition technique has particular application in forming the active region of a transistor.Type: ApplicationFiled: December 22, 2006Publication date: June 26, 2008Inventors: Michael L. Chabinyc, William S. Wong
-
Patent number: 7361529Abstract: A transistor is formed by applying modifier coatings to source and drain contacts and/or to the channel region between those contacts. The modifier coatings are selected to adjust the surface energy pattern in the source/drain/channel region such that semiconductor printing fluid is not drawn away from the channel region. For example, the modifier coatings for the contacts can be selected to have substantially the same surface energy as the modifier coating for the channel region. Semiconductor printing fluid deposited on the channel region therefore settles in place (due to the lack of a surface energy differential) and forms a relatively thick active semiconductor region between the contacts. Alternatively, the modifier coatings can be selected to have lower surface energies than the modifier coating in the channel region, which actually causes semiconductor printing fluid to be drawn towards the channel region.Type: GrantFiled: January 12, 2006Date of Patent: April 22, 2008Assignee: Palo Alto Research Center IncorporatedInventors: Michael L. Chabinyc, Ana C. Arias
-
Patent number: 7358530Abstract: An improved transistor array for a display or sensor device is described. The display or sensor device includes a plurality of pixels. Each pixel includes a width and a length. Each pixel is addressed by a transistor. The transistor addressing each pixel has a channel with a channel width. Each channel width is greater than the width or length of the pixel being addressed. By fabricating transistors with extremely long channel widths, lower mobility semiconductor materials can easily be used to fabricate the display device.Type: GrantFiled: December 12, 2003Date of Patent: April 15, 2008Assignee: Palo Alto Research Center IncorporatedInventors: William S. Wong, Jeng Ping Lu, Alberto Salleo, Michael L. Chabinyc, Raj B. Apte, Robert A. Street
-
Patent number: 7327774Abstract: A Vertical Cavity Surface Emitting Laser (VCSEL) assembly including a VCSEL structure having a light-emitting region located on its surface, a relatively wettable region of a surface modifier coating formed over the light emitting region, and a microlens formed on the relatively wettable region. A relatively non-wettable region of the surface modifier coating is formed around the light-emitting region (e.g., on the electrode surrounding the light-emitting region). The surface modifier coating is formed, for example, from one or more organothiols that change the surface energies of the light-emitting region and/or the electrode to facilitate self-assembly and self-registration of the microlens material. The microlens material is printed, microjetted, or dip coated onto the VCSEL structure such that the microlens material wets to the relatively wettable region, thereby forming a liquid bead that is reliably positioned over the light-emitting region. The liquid bead is then cured to form the microlens.Type: GrantFiled: December 17, 2004Date of Patent: February 5, 2008Assignee: Palo Alto Research Center IncorporatedInventors: Michael L. Chabinyc, Patrick Y. Maeda, Christopher L. Chua
-
Patent number: 7223700Abstract: A method and system for masking a surface to be etched is described. The method includes the operation of heating a phase-change masking material and using a droplet source to eject droplets of a masking material for deposit on a thin-film or other substrate surface to be etched. The temperature of the thin-film or substrate surface is controlled such that the droplets rapidly freeze after upon contact with the thin-film or substrate surface. The thin-film or substrate is then treated to alter the surface characteristics, typically by depositing a self assembled monolayer on the surface. After deposition, the masking material is removed. A material of interest is then deposited over the substrate such that the material adheres only to regions not originally covered by the mask such that the mask acts as a negative resist. Using such techniques, feature sizes of devices smaller than the smallest droplet printed may be fabricated.Type: GrantFiled: October 14, 2005Date of Patent: May 29, 2007Assignee: Palo Alto Research Center IncorporatedInventors: William S. Wong, Steven E. Ready, Stephen D. White, Alberto Salleo, Michael L. Chabinyc
-
Patent number: 7136216Abstract: A novel method of sealing ink in a microcell is described. A microcell is formed and an ink deposited in the microcell. A pressure sensitive tape seals the microcell. Ultraviolet light changes the properties of the adhesive in the pressure sensitive tape such that the material deposited in the microcell does not adhere to the adhesive. The described method is particularly useful for forming display structures.Type: GrantFiled: December 15, 2005Date of Patent: November 14, 2006Assignee: Palo Alto Research Center IncorporatedInventors: Jurgen H. Daniel, Michael L. Chabinyc
-
Patent number: 7129181Abstract: Controlled overetching is utilized to produce metal patterns having gaps that are smaller than the resolution limits of the feature patterning (e.g., photolithography) process utilized to produce the metal patterns. A first metal layer is formed and masked, and exposed regions are etched away. The etching process is allowed to continue in a controlled manner to produced a desired amount of over-etching (i.e., undercutting the mask) such that an edge of the first metal layer is offset from an edge of the mask by a predetermined gap distance. A second metal layer is then deposited such that an edge of the second metal layer is spaced from the first metal layer by the predetermined gap distance. The metal gap is used to define, for example, transistor channel lengths, thereby facilitating the production of transistors having channel lengths defined by etching process control that are smaller than the process resolution limits.Type: GrantFiled: September 17, 2004Date of Patent: October 31, 2006Assignee: Palo Alto Research Center IncorporatedInventors: JengPing Liu, Jackson H. Ho, Chinnwen Shih, Michael L. Chabinyc, William S. Wong
-
Patent number: 7125495Abstract: Two different processing techniques are utilized to respectively form high resolution features and low resolution features in a critical layer of an electronic device, and in particular a large area electronic device. High resolution features are formed by soft lithography, and low resolution features are formed by jet-printing or using a jet-printed etch mask. Jet-printing is also used to stitch misaligned structures. Alignment marks are generated with the features to coordinate the various processing steps and to automatically control the stitching process. Thin-film transistors are formed by generating gate structures using a first jet-printed etch mask, forming source/drain electrodes using soft lithography, forming interconnect structures using a second jet-printed etch mask, and then depositing semiconductor material over the source/drain electrodes.Type: GrantFiled: December 20, 2004Date of Patent: October 24, 2006Assignee: Palo Alto Research Center, Inc.Inventors: Robert A. Street, William S. Wong, Alberto Salleo, Michael L. Chabinyc
-
Patent number: 7087444Abstract: A method of forming an integrated microelectronic device and a micro channel is provided. The method offers an inexpensive way of integrating devices that are usually incompatible during fabrication, a microchannel and a microelectronic structure such as an electro-optic light source, a detector or a MEMs device into a single integrated structure.Type: GrantFiled: December 16, 2002Date of Patent: August 8, 2006Assignee: Palo Alto Research Center IncorporatedInventors: William S. Wong, Michael L. Chabinyc, Steven E. Ready, Michael A. Kneissl, Mark R. Teepe
-
Patent number: 7019328Abstract: A transistor is formed by applying modifier coatings to source and drain contacts and/or to the channel region between those contacts. The modifier coatings are selected to adjust the surface energy pattern in the source/drain/channel region such that semiconductor printing fluid is not drawn away from the channel region. For example, the modifier coatings for the contacts can be selected to have substantially the same surface energy as the modifier coating for the channel region. Semiconductor printing fluid deposited on the channel region therefore settles in place (due to the lack of a surface energy differential) and forms a relatively thick active semiconductor region between the contacts. Alternatively, the modifier coatings can be selected to have lower surface energies than the modifier coating in the channel region, which actually causes semiconductor printing fluid to be drawn towards the channel region.Type: GrantFiled: June 8, 2004Date of Patent: March 28, 2006Assignee: Palo Alto Research Center IncorporatedInventors: Michael L. Chabinyc, Ana C. Arias
-
Patent number: 6921679Abstract: An electronic device and a method of fabricating the electronic device includes forming a first electrical contact, a dielectric layer and a second electrical contact wherein the dielectric layer is located between the first and the second electrical contacts, forming an electrically insulating layer over the dielectric layer and the first electrical contact, exposing the first and second electrical contact, the dielectric layer and a first portion of the electrically insulating layer to radiation from the side of the first electrical contact, removing a second portion of the electrically insulating layer that was not irradiated by the radiation, providing a semiconductor material over a portion of the dielectric layer, and forming at least a third electrical contact over at least a portion of the electrically insulating layer and the semiconductor material.Type: GrantFiled: December 19, 2003Date of Patent: July 26, 2005Assignee: Palo Alto Research Center IncorporatedInventors: Michael L Chabinyc, Alberto Salleo, William S. Wong
-
Patent number: 6872588Abstract: A structure and method of using microfluidic channels to form an array of semiconductor devices is described. The microfluidic channels have been found to be particularly useful when formed in a self aligned process and used to interconnect a series of thin film transistor (TFT) devices.Type: GrantFiled: November 22, 2002Date of Patent: March 29, 2005Assignee: Palo Alto Research Center Inc.Inventors: Michael L. Chabinyc, William S. Wong, Robert A. Street, Kateri E. Paul
-
Patent number: 6759713Abstract: A structure and method of using microfluidic channels to form an array of semiconductor devices is described. The microfluidic channels have been found to be particularly useful when formed in a self aligned process and used to interconnect a series of thin film transistor (TFT) devices.Type: GrantFiled: November 22, 2002Date of Patent: July 6, 2004Assignee: Xerox CorporationInventors: Michael L. Chabinyc, William S. Wong, Kateri E. Paul, Robert A. Street
-
Publication number: 20040115861Abstract: A method of forming an integrated microelectronic device and a micro channel is provided. The method offers an inexpensive way of integrating devices that are usually incompatible during fabrication, a microchannel and a microelectronic structure such as an electro-optic light source, a detector or a MEMs device into a single integrated structure.Type: ApplicationFiled: December 16, 2002Publication date: June 17, 2004Applicant: Palo Alto Research Center IncorporatedInventors: William S. Wong, Michael L. Chabinyc, Steven E. Ready, Michael A. Kneissl, Mark R. Teepe
-
Publication number: 20040099911Abstract: A structure and method of using microfluidic channels to form an array of semiconductor devices is described. The microfluidic channels have been found to be particularly useful when formed in a self aligned process and used to interconnect a series of thin film transistor (TFT) devices.Type: ApplicationFiled: November 22, 2002Publication date: May 27, 2004Applicant: Xerox Corporation.Inventors: Michael L. Chabinyc, William S. Wong, Kateri E. Paul, Robert A. Street
-
Publication number: 20040101987Abstract: A structure and method of using microfluidic channels to form an array of semiconductor devices is described. The microfluidic channels have been found to be particularly useful when formed in a self aligned process and used to interconnect a series of thin film transistor (TFT) devices.Type: ApplicationFiled: November 22, 2002Publication date: May 27, 2004Applicant: Xerox Corporation.Inventors: Michael L. Chabinyc, William S. Wong, Robert A. Street, Kateri E. Paul