Abstract: A system for converting a floating point n-bit signed magnitude binary number to a fixed point two's complement binary number having m bits wherein m is greater than n, first converts the n bit signed magnitude binary number to a corresponding n-bit two's complement binary number. Thereafter, a shifter shifts the n-bit two's complement binary number to the left or right and by a number of bits responsive to received shift decode signals for providing the final fixed point m-bit two's complement binary number.

Abstract: A read-only memory for storing a plurality of bits of information. The read-only memory includes a plurality of memory cells arranged in an array with each memory cell including a capacitor having either a relatively high capacitance or a relatively low capacitance representing a bit of stored information. The read-only memory further includes a reading means for accessing each memory cell and providing a first or second output responsive to the capacitance level of the memory cell capacitance means.

Abstract: A modular test structure for performing testing on a single chip having a plurality of different functional blocks is provided which includes test interface logic circuitry (24) formed on each of the functional blocks (16-22) so that each block can be operated as a self-contained module. Test generation logic circuitry (40) is formed in a bus interface unit (12) and is used to select one or more of the functional blocks (16-22) for testing and for placing the selected functional blocks (16-22) in a test mode. The test interface logic circuitry (24) on the selected functional blocks under test sends data direction information to the bus interface unit (12) to indicate how individual bits of a data bus are to be used for inputs and outputs during testing.

Abstract: A TTL output driver gate configuration which has reduced voltage spikes on internal power supply potential and ground potential nodes includes a P-channel pull-up transistor (P1), an N-channel pull-down transistor (N1), a NAND logic gate (14), a NOR logic gate (16), a first positive feedback amplifier circuit (18), and a second positive feedback amplifier circuit (20). The pull-up transistor (P1) and the pull-down transistor (N1) have gates which are made serpentine. The reduction of voltage spikes is achieved by slowing down the turn-on times of the pull-up and pull-down transistors during transitions due to the distributed resistances and capacitances of the polysilicon material used to form the serpentine gates thereof. The first and second positive feedback amplifier circuits (18, 20) are used to pull the undriven gate ends of the respective transistors all the way to negative and positive supply potentials so as to facilitate transitions at an output node.

Abstract: An asynchronous interrupt status bit circuit for use in conjunction with a microprocessor, which guarantees that no interrupting conditions are missed and that no single interrupting condition is indicated twice, includes a master latch (12), a transfer gate (14), a clocked latch (16), an inverter (18), an output driver circuit (20), and a clearing circuit (22, 24). The master latch (12) is responsive to an interrupt input signal for generating an interrupting logic signal at its output which is latched to a low logic level. The clearing circuit (22, 24) is responsive to a control signal for generating a clear signal to clear the output of the master latch (12) to a high level only when the control signal is latched at a high level before the time a true read signal is making a high-to-low transition. The next read signal causes an output signal having a low level to be read by the microprocessor if no interrupt input signal has occured.

Abstract: An asynchronous interrupt status bit circuit for use in conjunction with a microprocessor, which guarantees that no interrupting conditions are missed and that no single interrupting condition is indicated twice, includes a master latch (12), a transfer gate (14), a clocked latch (16), an inverter (18), an output driver circuit (20), and a clearing circuit (22, 24). The master latch (12) is responsive to an interrupt input signal for generating an interrupting logic signal at its output which is latched to a low logic level. The clearing circuit (22, 24) is responsive to a control signal for generating a clear signal to clear the output of the master latch (12) to a high level only when the control signal is latched at a high level before the time a true read signal is making a high-to-low transition. The next read signal causes an output signal having a low level to be read by the microprocessor if no interrupt input signal has occurred.