Abstract: A tunable capacitor may include a first terminal having a first semiconductor component with a first polarity. The tunable capacitor may also include a second terminal having a second semiconductor component with a second polarity. The second component may be adjacent to the first semiconductor component. The tunable capacitor may further include a first conductive material electrically coupled to a first depletion region at a first sidewall of the first semiconductor component.

Abstract: A device includes a substrate, a first nanowire field effect transistor (FET), and a second nanowire FET positioned between the substrate and the first nanowire FET. The device also includes a first nanowire electrically coupled to the first nanowire FET and to the second nanowire FET.

Abstract: A system for locating an asset can include a first light fixture disposed in a volume of space and having a first transceiver, a first light source, and a first modulation circuit, where the first light source emits a first light output that defines a first line of sight, where the first modulation circuit generates and sends a first VLC signal that is part of the first light output, where a first light fixture location of the first light fixture in the volume of space is previously determined using the first transceiver during an auto-commissioning process. The system can also include a communication device associated with the asset, where the asset is disposed in the volume of space, where the communication device includes a second transceiver, where the second transceiver receives the first VLC signal from the first transceiver.

Abstract: An embodiment of a system and method of surveying users on a social networking system is described which limits the frequency in which any one user is surveyed. Users are assigned into a multi-layered survey pool based on a hash value derived from a user identification number for the online social network that is assigned to the user. Users are randomly offered the opportunity to take a survey, and the subject matter of the survey is at least partially determined by the layer from which the survey obtains its sample populace.

Abstract: An apparatus is disclosed that includes a frequency multiplexer circuit coupled to an input node and configured to receive an input signal via the input node. The frequency multiplexer circuit comprises a first filter circuit, a second filter circuit, and a third filter circuit. The apparatus also includes a switching circuit that is configurable to couple at least two of a first output of the first filter circuit, a second output of the second filter circuit, or a third output of the third filter circuit to a single output port.

Abstract: Disclosed is a heterojunction bipolar transistor, and method of manufacturing the same, including an emitter having a conductive emitter contact coupled to a first side of the emitter, a first side of a base coupled to a second side of the emitter opposite the first side of the emitter, a collector coupled to the base on a second side of the base opposite the emitter, wherein an area of a junction between the base and the collector is less than or equal to an area of a junction between the base and the emitter, a first conductive base contact coupled to the base, and a conductive collector contact coupled to the collector on the side of the collector opposite the emitter and substantially parallel to the first conductive base contact.

Abstract: Examples of monolithic integrated emitter-detector array in a flexible substrate for biometric sensing and associated devices and methods are disclosed. One disclosed example device includes a flexible substrate; a first array of emitters embedded in the flexible substrate, the first array of emitters configured to emit first electromagnetic (EM) signals; a first array of detectors embedded in the flexible substrate, the first array of detectors configured to detect reflections of the first EM signals; a first scanning circuit coupled to the first array of emitters, the first scanning circuit configured to selectively activate individual emitters of the first array of emitters; and a first sensing circuit coupled to individual detectors of the first array of detectors, the first sensing circuit configured to receive a detection signal from at least one of the detectors of the first array of detectors.

Abstract: Self-aligned metal cut and via for Back-End-Of-Line (BEOL) processes for semiconductor integrated circuit (IC) fabrication, and related processes and devices, is disclosed. In this manner, mask placement overlay requirements can be relaxed. This relaxation can be multiples of that allowed by conventional BEOL techniques. This is enabled through application of different fill materials for alternating lines in which a conductor will later be placed. With these different fill materials in place, a print cut and via mask is used, with the mask allowed to overlap other adjacent fill lines to that of the desired line. Etching is then applied that is selective to the desired line but not adjacent lines.

Abstract: An integrated circuit (IC) includes a first semiconductor device on a glass substrate. The first semiconductor device includes a first semiconductive region of a bulk silicon wafer. The IC includes a second semiconductor device on the glass substrate. The second semiconductor device includes a second semiconductive region of the bulk silicon wafer. The IC includes a through substrate trench between the first semiconductive region and the second semiconductive region. The through substrate trench includes a portion disposed beyond a surface of the bulk silicon wafer.

Abstract: A social networking system obtains linguistic data from a user's text communications on the social networking system. For example, occurrences of words in various types of communications by the user in the social networking system are determined. The linguistic data and non-linguistic data associated with the user are used in a trained model to predict one or more personality characteristics for the user. The inferred personality characteristics are stored in connection with the user's profile, and may be used for targeting, ranking, selecting versions of products, and various other purposes.

Abstract: A device includes a substrate, a first nanowire field effect transistor (FET), and a second nanowire FET positioned between the substrate and the first nanowire FET. The device also includes a first nanowire electrically coupled to the first nanowire FET and to the second nanowire FET.

Abstract: A nanowire transistor is provided that includes a well implant having a local isolation region for insulating a replacement metal gate from a parasitic channel. In addition, the nanowire transistor includes oxidized caps in the extension regions that inhibit parasitic gate-to-source and gate-to-drain capacitances.

Abstract: Isolated complementary metal-oxide semiconductor (CMOS) devices for radio-frequency (RF) circuits are disclosed. In some aspects, an RF circuit includes CMOS devices, a silicon substrate having doped regions that define the CMOS devices, and a trench through the silicon substrate. The trench through the silicon substrate forms a continuous channel around the doped regions of one of the CMOS devices to electrically isolate the CMOS device from other CMOS devices embodied on the silicon substrate. By so doing, performance characteristics of the CMOS device, such as linearity and signal isolation, may be improved over those of conventional CMOS devices (e.g., bulk CMOS).

Abstract: An apparatus includes a varactor having a first contact that is located on a first side of a substrate. The varactor includes a second contact that is located on a second side of the substrate, and the second side is opposite the first side. The apparatus further includes a signal path between the first contact and the second contact.

Abstract: Self-aligned metal cut and via for Back-End-Of-Line (BEOL) processes for semiconductor integrated circuit (IC) fabrication, and related processes and devices, is disclosed. In this manner, mask placement overlay requirements can be relaxed. This relaxation can be multiples of that allowed by conventional BEOL techniques. This is enabled through application of different fill materials for alternating lines in which a conductor will later be placed. With these different fill materials in place, a print cut and via mask is used, with the mask allowed to overlap other adjacent fill lines to that of the desired line. Etching is then applied that is selective to the desired line but not adjacent lines.

Abstract: Isolated complementary metal-oxide semiconductor (CMOS) devices for radio-frequency (RF) circuits are disclosed. In some aspects, an RF circuit includes CMOS devices, a silicon substrate having doped regions that define the CMOS devices, and a trench through the silicon substrate. The trench through the silicon substrate forms a continuous channel around the doped regions of one of the CMOS devices to electrically isolate the CMOS device from other CMOS devices embodied on the silicon substrate. By so doing, performance characteristics of the CMOS device, such as linearity and signal isolation, may be improved over those of conventional CMOS devices (e.g., bulk CMOS).

Abstract: Ground shielding is achieved by a conductor shield having conductive surfaces that immediately surround individual chips within a fan-out wafer level package (FOWLP) module or device. Intra-module shielding between individual chips within the FOWLP module or device is achieved by electromagnetic or radio-signal (RF) isolation provided by the surfaces of the conductor shield immediately surrounding each of the chips. The conductor shield is directly connected to one or more grounded conductor portions of a FOWLP to ensure reliable grounding.

Abstract: An integrated circuit (IC) includes a glass substrate and a buried oxide layer. The IC additionally includes a first semiconductor device coupled to the glass substrate. The first semiconductor device includes a first gate and a first portion of a semiconductive layer coupled to the buried oxide layer. The first gate is located between the glass substrate and the first portion of the semiconductive layer and between the glass substrate and the buried oxide layer. The IC additionally includes a second semiconductor device coupled to the glass substrate. The second semiconductor device includes a second gate and a second portion of the semiconductive layer. The second gate is located between the glass substrate and the second portion of the semiconductive layer. The first portion is discontinuous from the second portion.

Abstract: Substrate-transferred, deep trench isolation silicon-on-insulator (SOI) semiconductor devices formed from bulk semiconductor wafers are disclosed. In this regard, a bulk semiconductor wafer is provided that includes a bulk body, one or more transistors formed in the bulk body, and deep trenches formed between the transistors formed in the bulk body to provide isolation between the transistors. To prevent the bulk body from electrically interconnecting the transistors, the bulk body is thinned near, at, or beyond a back side of the deep trenches formed in the bulk body to form separate bulk bodies for each transistor isolated by the deep trenches. An insulation substrate is bonded to the bulk semiconductor device to form an SOI wafer. In this manner, residual bulk bodies of the transistors in the SOI wafer are isolated between the deep trenches and the insulation substrate to reduce or avoid leakage current between transistors.

Abstract: An integrated circuit (IC) includes a first semiconductor device on a glass substrate. The first semiconductor device includes a first semiconductive region of a bulk silicon wafer. The IC includes a second semiconductor device on the glass substrate. The second semiconductor device includes a second semiconductive region of the bulk silicon wafer. The IC includes a through substrate trench between the first semiconductive region and the second semiconductive region. The through substrate trench includes a portion disposed beyond a surface of the bulk silicon wafer.