Patents by Inventor Michael Parkin

Michael Parkin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110129348
    Abstract: A method of forming a composite airfoil having a suction side and pressure side includes the steps of designing a mold, designing a woven core, designing a plurality of plies and assembling the designed mold, core and plies to create the composite airfoil. The hollow mold has an inner surface which defines the surface profile of the composite airfoil. The plurality of plies is designed to fit between the inner surface of the mold and an outer surface of the woven core. The plurality of plies is designed after the step of designing the woven core.
    Type: Application
    Filed: November 30, 2009
    Publication date: June 2, 2011
    Applicant: UNITED TECHNOLOGIES CORPORATION
    Inventors: Michael Parkin, Phillip Alexander, Brian P. Huth, Carl Brian Klinetob
  • Patent number: 7947963
    Abstract: A method of measuring radioactivity includes determining a fitted spectral distribution region for recorded counts data of at least a first activity peak determining characteristic data of the fitted spectral distribution region, and using the characteristic data to determine a spectral distribution region of a second activity peak.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: May 24, 2011
    Assignee: Laboratory Impex Systems Ltd.
    Inventor: James Michael Parkin
  • Publication number: 20110052405
    Abstract: A composite airfoil has a root, a tip, a root region and a tip region. The composite airfoil further includes a woven core, a first filament reinforced airfoil ply, a second filament reinforced airfoil ply and a local reinforcement laminate section. The woven core extends from the root to the tip of the composite airfoil. The first filament reinforced airfoil ply is stacked on the woven core and the second filament reinforced airfoil ply is stacked adjacent to the first filament reinforced airfoil ply on the woven core. The local reinforcement laminate section is at the tip region of the composite airfoil and comprises a first reinforcement ply that does not extend to the root region. The local reinforcement laminate section increases a chordwise flexural stiffness of the tip region.
    Type: Application
    Filed: September 2, 2009
    Publication date: March 3, 2011
    Applicant: UNITED TECHNOLOGIES CORPORATION
    Inventor: Michael Parkin
  • Publication number: 20110038732
    Abstract: The disclosed composite airfoil includes a three-dimensional composite core extending longitudinally and having a chord-wise direction. The core has a core in-plane thickness extending between opposing sides in a through-plane direction generally perpendicular to the chord-wise and longitudinal directions. A composite skin covers the opposing sides and has an exterior surface providing an airfoil contour. The skin includes a total skin in-plane thickness corresponding to a sum of thicknesses through the skin in the through-plane direction from each of the opposing sides to their adjoining exterior surface. A sum of the core in-plane and total skin in-plane thicknesses at a central portion of the composite airfoil is a total in-plane thickness. The total skin in-plane thickness at the central portion is less than 50% of the total in-plane thickness.
    Type: Application
    Filed: August 14, 2009
    Publication date: February 17, 2011
    Inventors: Brian P. Huth, Phillip Alexander, Carl Brian Klinetob, Michael Parkin, Rajiv A. Naik
  • Publication number: 20100254821
    Abstract: An intermediate-manufactured composite airfoil includes first and second composite skins each having a plurality of fibers in a polymer matrix. A composite core is removably located between the first and second composite skins. The composite core includes a dry, three-dimensional, woven fiber network. The composite core may alternatively include a three-dimensional, woven fiber network in a fully cured polymer matrix.
    Type: Application
    Filed: April 6, 2009
    Publication date: October 7, 2010
    Inventors: Michael Parkin, Phillip Alexander, Carl Brian Klinetob, Steven Clarkson
  • Publication number: 20100059685
    Abstract: A method of measuring radioactivity includes determining a fitted spectral distribution region for recorded counts data of at least a first activity peak determining characteristic data of the fitted spectral distribution region, and using the characteristic data to determine a spectral distribution region of a second activity peak.
    Type: Application
    Filed: July 30, 2009
    Publication date: March 11, 2010
    Applicant: Laboratory Impex Systems, Ltd.
    Inventor: James Michael Parkin
  • Publication number: 20090075038
    Abstract: The present invention relates to a printing formulation comprising monodisperse particles and particles, wherein the particles have a largest dimension which is at least 6 times larger than the largest dimension of the monodisperse particles, as well as to the use of these formulations for printing and to substances printed with these formulations.
    Type: Application
    Filed: August 27, 2008
    Publication date: March 19, 2009
    Inventors: Michael Francis Butler, John William Davison, Ramin Djalali, Philip Michael Parkins
  • Publication number: 20080075730
    Abstract: This disclosure relates to methods and compositions to regulate biofilm formation. In particular, the disclosure provides methods and compositions that relate to regulation of biofilm formation by modulating the GacA/GacS regulatory system as well as methods and compositions for inhibiting small colony variant formation and reversion of resistant bacteria to a wild-type phenotype.
    Type: Application
    Filed: January 12, 2007
    Publication date: March 27, 2008
    Applicant: University Technologies International Inc.
    Inventors: Douglas Storey, Michael Parkins, Howard Ceri, James Davies, Merle Olson, Lyriam Marques
  • Publication number: 20070292465
    Abstract: Binary or greater mixtures of biocides which exist in the form of eutectic blends which range from damp blends to liquid blends are described. Mixtures of phenolic biocides are preferred. The biocides are useful in the formulation of disinfectant compositions for industrial and domestic use.
    Type: Application
    Filed: June 16, 2006
    Publication date: December 20, 2007
    Inventors: Michael Parkin, Uwe Falk, Cezanne Vielkanowitz
  • Publication number: 20070079930
    Abstract: A sizable reduced weight bicycle frame and method for making such incorporating tubes of a composite material, the method providing for flexibility and full customization of the bicycle frame with a minimum amount of tooling, which tooling securely holds lugs of the bicycle frame at selected customized positions relative to the tooling during the molding process.
    Type: Application
    Filed: December 12, 2006
    Publication date: April 12, 2007
    Applicant: CANNONDALE BICYCLE CORPORATION
    Inventor: Michael Parkin
  • Patent number: 7080234
    Abstract: According to the invention, a processing core (12) comprising a processing pipeline (100) having N-number of processing paths (56), each of which process instructions (54) on M-bit data words. In addition, the processing core (12) includes one or more register files (60), each preferably having Q-number of registers which are M-bits wide. Preferably, one of the Q-number of registers in at least one of the register files (60) is a program counter register dedicated to hold a program counter, and one of the Q-number of registers in at least one of the register files is a zero register dedicated to hold a zero value. In this manner, program jumps can be executed by adding values to the program counter in the program counter register, and memory address values can be calculated by adding values to the program counter stored in the program counter register or to the zero value stored in the zero register.
    Type: Grant
    Filed: March 8, 2001
    Date of Patent: July 18, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Ashley Saulsbury, Nyles Nettleton, Michael Parkin, David R. Emberson
  • Patent number: 7020763
    Abstract: A processing core comprising R-number of processing pipelines each comprising N-number of processing paths. Each of the R-number of processing pipelines are synchronized together to operate as a single very long instruction word (VLIW) processing core. The VLIW processing core is configured to process R×N-number of VLIW sub-instructions in parallel. In addition, the R-number of pipelines can be configured to operate independently as separately operating pipelines. In accordance with one embodiment of the present invention, each of the R-number of processing pipelines comprises S-number of register files, such that the processing core comprises R×S-number of register files. In accordance with another embodiment of the present invention, each of the R-number of processing pipelines comprises one register file for every two of the N-number of processing paths, such that S=N/2.
    Type: Grant
    Filed: March 8, 2001
    Date of Patent: March 28, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Ashley Saulsbury, Michael Parkin, Daniel S. Rice
  • Publication number: 20060038375
    Abstract: A sizable reduced weight bicycle frame and method for making such incorporating tubes of a composite material, the method providing for flexibility and full customization of the bicycle frame with a minimum amount of tooling, which tooling securely holds lugs of the bicycle frame at selected customized positions relative to the tooling during the molding process.
    Type: Application
    Filed: June 30, 2004
    Publication date: February 23, 2006
    Inventor: Michael Parkin
  • Patent number: 6988181
    Abstract: According to the invention, a processing core is disclosed. The processing core includes one or more processing pipelines and a number of register flies. The processing pipelines having a total of N-number of processing paths, where each of the processing paths processes instructions on M-bit data words. Each of the number of register files has Q-number of registers that are each M-bits wide. The Q-number of registers within each of the plurality of register files are either private or global registers. When a value is written to one of said Q-number of said registers, which is a global register within one of said number of register files, the value is propagated to a corresponding global register in the other of the number of register files. When a value is written to one of said Q-number of the registers, which is a private register within one of said number of register files, the value is not propagated to a corresponding register in the other of said number of register files.
    Type: Grant
    Filed: March 8, 2001
    Date of Patent: January 17, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Ashley Saulsbury, Michael Parkin, Daniel S. Rice
  • Publication number: 20050151344
    Abstract: A structural member (38, 40) is designed to have a first portion having a first composite layup, a second portion having a second composite layup, and at least one center portion having at least a third composite layup such that it can flex near a desired point of the structural member. The structural member may be used as a chain stay (26) in a bicycle frame (10). The chain stays are designed to have a geometry that will allow for flexing or bending at or in the vicinity of a desired point. They may be pre-loaded for flex in both a positive and negative direction. The chain stays are designed having a varying cross sectional area. The bending or flexing location of the chain stays has a narrower height from the side view than the ends of the chain stay allowing the chain stay to flex. Additionally, the bending or flexing location has a wider width from the top view than the ends of the chain stay for additional torsional and lateral stiffness.
    Type: Application
    Filed: January 14, 2005
    Publication date: July 14, 2005
    Inventor: Michael Parkin
  • Patent number: 6631439
    Abstract: A novel processor chip (10) having a processing core (12), at least one bank of memory (14), an I/O link (26) configured to communicate with other like processor chips or compatible I/O devices, a memory controller (20) in electrical communication with processing core (12) and memory (14), and a distributed shared memory controller (22) in electrical communication with memory controller (20) and I/O link (26). Distributed shared memory controller (22) is configured to control the exchange of data between processor chip (10) and the other processor chips or I/O devices. In addition, memory controller (20) is configured to receive memory requests from processing core (12) and distributed shared memory controller (22) and process the memory request with memory (14). Processor chip (10) may further comprise an external memory interface (24) in electrical communication with memory controller (20). External memory interface (24) is configured to connect processor chip (10) with external memory, such as DRAM.
    Type: Grant
    Filed: March 8, 2001
    Date of Patent: October 7, 2003
    Assignee: Sun Microsystems, Inc.
    Inventors: Ashley Saulsbury, Nyles Nettleton, Michael Parkin
  • Publication number: 20020087821
    Abstract: According to the invention, a first processor chip (10) comprising a processing core (12) and at least one bank of memory (14). The at least one bank of memory (14) preferably includes a mode control input (32) for controlling the mode of the at least one bank of memory (14) between physical memory and cache memory. In addition, the first processor chip (10) may further comprise an I/O link (26) configured to facilitate communication between the first processor chip (10) and other processor chips, and a communication and memory controller (20, 22) in electrical communication with the processing core (12), the at least one bank of memory (14), and the I/O link (26).
    Type: Application
    Filed: March 8, 2001
    Publication date: July 4, 2002
    Inventors: Ashley Saulsbury, Nyles Nettleton, Michael Parkin, David R. Emberson
  • Publication number: 20020049892
    Abstract: A processing core comprising R-number of processing pipelines each comprising N-number of processing paths. Each of the R-number of processing pipelines are synchronized together to operate as a single very long instruction word (VLIW) processing core. The VLIW processing core is configured to process R×N-number of VLIW sub-instructions in parallel. In addition, the R-number of pipelines can be configured to operate independently as separately operating pipelines. In accordance with one embodiment of the present invention, each of the R-number of processing pipelines comprises S-number of register files, such that the processing core comprises R×S-number of register files. In accordance with another embodiment of the present invention, each of the R-number of processing pipelines comprises one register file for every two of the N-number of processing paths, such that S=N/2.
    Type: Application
    Filed: March 8, 2001
    Publication date: April 25, 2002
    Inventors: Ashley Saulsbury, Michael Parkin, Daniel S. Rice
  • Publication number: 20020032849
    Abstract: According to the invention, a processing core (12) comprising a processing pipeline (100) having N-number of processing paths (56), each of which process instructions (54) on M-bit data words. In addition, the processing core (12) includes one or more register files (60), each preferably having Q-number of registers which are M-bits wide. Preferably, one of the Q-number of registers in at least one of the register files (60) is a program counter register dedicated to hold a program counter, and one of the Q-number of registers in at least one of the register files is a zero register dedicated to hold a zero value. In this manner, program jumps can be executed by adding values to the program counter in the program counter register, and memory address values can be calculated by adding values to the program counter stored in the program counter register or to the zero value stored in the zero register.
    Type: Application
    Filed: March 8, 2001
    Publication date: March 14, 2002
    Inventors: Ashley Saulsbury, Nyles Nettleton, Michael Parkin, David Emberson
  • Publication number: 20020032831
    Abstract: A novel processor chip (10) having a processing core (12), at least one bank of memory (14), an I/O link (26) configured to communicate with other like processor chips or compatible I/O devices, a memory controller (20) in electrical communication with processing core (12) and memory (14), and a distributed shared memory controller (22) in electrical communication with memory controller (20) and I/O link (26). Distributed shared memory controller (22) is configured to control the exchange of data between processor chip (10) and the other processor chips or I/O devices. In addition, memory controller (20) is configured to receive memory requests from processing core (12) and distributed shared memory controller (22) and process the memory request with memory (14). Processor chip (10) may further comprise an external memory interface (24) in electrical communication with memory controller (20). External memory interface (24) is configured to connect processor chip (10) with external memory, such as DRAM.
    Type: Application
    Filed: March 8, 2001
    Publication date: March 14, 2002
    Inventors: Ashley Saulsbury, Nyles Nettleton, Michael Parkin