Abstract: According to the invention, a processing core (12) comprising one or more processing pipelines (100) having N-number of processing paths (56), each of which process instructions (54) on M-bit data words. In addition, the processing core (12) includes a plurality of register files (60), each preferably having Q-number of registers which are M-bits wide. Preferably, every two of the processing paths (56) share one register file (60). A processing instruction (52) preferably comprises N-number of P-bit instructions (54) appended together to form a very long instruction word (VLIW), and the N-number of processing paths (56) preferably process the N-number of P-bit instructions (54) in parallel. In accordance with one preferred embodiment of the invention, M is 64, Q is 64 and P is 32. Accordingly, the N-number of processing paths (56), each process 32-bit instructions (54) on 64-bit data words, and the plurality of register files (60) each have 64 registers which are 64-bits wide.