Abstract: A control component implements pipelined data processing operations in either of two timing domains bridged by a domain-crossing circuit according to one or more configuration signals that indicate relative clock frequencies of the two domain and/or otherwise indicate which of the two timing domains will complete the data processing operations with lowest latency.

Abstract: An interconnected stack of one or more Dynamic Random Access Memory (DRAM) die also has one or more custom logic, controller, or processor die. The custom die(s) of the stack include direct channel interfaces that allow direct access to memory regions on one or more DRAMs in the stack. The direct channels are time-division multiplexed such that each DRAM die is associated with a time slot on a direct channel. The custom die configures a first DRAM die to read a block of data and transmit it via the direct channel using a time slot that is assigned to a second DRAM die. The custom die also configures the second memory device to receive the first block of data in its assigned time slot and write the block of data.

Abstract: Provided herein is a film and methods of producing the same. The film includes a substrate and a layer adjacent to the substrate, wherein a surface of the layer comprises spaced apart protrusions. The methods include providing a substrate, depositing a layer on at least a portion of the substrate, decomposing the layer to form at least a first phase of material and a second phase of material, and removing at least a portion of the second phase from the decomposed layer to form a structured layer.

Abstract: Disclosed is a dynamic random access memory that has columns, data rows, tag rows and comparators. Each comparator compares address bits and tag information bits from the tag rows to determine a cache hit and generate address bits to access data information in the DRAM as a multiway set associative cache.

Abstract: An acoustic treatment for use in an acoustic treatment for a gas turbine engine includes a sheath having a plurality of perforations. A plurality of cell structures extends from the sheath such that the sheath and the cell structures are a monolithic component. The plurality of perforations of the sheath are formed by filaments of a first material that define a first dimension of the perforations having a linear edge and filaments of a second material crossing the filaments of the first material that define a second dimension of the perforations having a linear edge. Such perforations have a non-cylindrical shape defined by the linear edges of the filaments of the first material and the filaments of the second material. A gas turbine engine is also disclosed.

Abstract: A method of forming a component utilizing material extrusion includes the steps of (1) delivering a hopper of particulate media formed of a primary material into an extruder, (2) selectively providing an infill material into the primary material within the extruder, (3) delivering a filament of the primary material and the infill material downstream to a nozzle where it is then deposited to form the component, and (4) a control associated with the nozzle selectively delivering the infill material into the primary material, or blocking a delivery of the infill material into the primary material dependent on an area in the component which is being formed.

Abstract: A system includes a top drive including a handling ring assembly including a main body, a main shaft that traverses the main body of the handling ring assembly. an internal blowout preventer (IBOP) valve, wherein the main shaft engages the IBOP valve. a two-piece actuator sleeve assembly including a non-rotating portion and a rotating portion, at least one hydraulic cylinder connected to the main body of the handling ring assembly, wherein the at least one hydraulic cylinder actuates the two-piece actuator sleeve assembly, and left and right hand crank assemblies having left and right wireless encoders connected thereto, wherein the crank assemblies with the wireless encoders are attached to, and are configured to rotate with, the IBOP valve along with the rotating portion of the two-piece actuator sleeve assembly.

Abstract: A method of forming a component by material extrusion includes the steps of forming a plurality of first filaments extending along at least a first axis of a three dimensional space and forming a plurality of second filaments crossing the plurality of first filaments by extending in a direction with at least a component along second and third axes in the three dimensional space.

Abstract: A method for interconnecting components of a hydraulic fracturing system using flexible hose or pipe. The flexible hose or pipe can form a singular flow line which interconnects, for example, a pump and a manifold of the hydraulic fracturing system. Each end of the flexible hose or pipe can be tethered (using a safety restraint) to another component of the hydraulic fracturing system. In the event of a rupture or other failure, the safety restraint retains the tethered flexible pipes or hoses in a fixed position to prevent injury to personnel or damage to surrounding equipment.

Abstract: A dynamic random access memory (DRAM) device includes functions configured to aid with operating the DRAM device as part of data caching functions. The DRAM is configured to respond to at least two types of commands. A first type of command (cache data access command) seeks to access a cache line of data, if present in the DRAM cache. A second type of command (cache probe command) seeks to determine whether a cache line of data is present, but is not requesting the data be returned in response. In response to these types of access commands, the DRAM device is configured to receive cache tag query values and to compare stored cache tag values with the cache tag query values. A hit/miss (HM) interface/bus may indicate the result of the cache tag compare and stored cache line status bits to a controller.

Abstract: A device, system, process, and method for extracting metals from contaminated fluid comprising a pretreatment stage, a biosorption column, a thermal dewatering processes, and at least one chemical precipitation step. The biosorption process typically involves at least one fixed bed column wherein metals are reversibly adsorbed to immobilized biomass and eluted with a caustic solution. Treated effluent is further processed via thermal dewatering and chemical precipitation. The process can be used to simultaneously purify industrial wastewater for reuse while extracting valuable metals.

Abstract: A multi-processor device is disclosed. The multi-processor device includes interface circuitry to receive requests from at least one host device. A primary processor is coupled to the interface circuitry to process the requests in the absence of a failure event associated with the primary processor. A secondary processor processes operations on behalf of the primary processor and selectively receives the requests from the interface circuitry based on detection of the failure event associated with the primary processor.

Abstract: A memory system includes two or more memory controllers capable of accessing the same dynamic, random-access memory (DRAM), one controller having access to the DRAM or a subset of the DRAM at a time. Different subsets of the DRAM are supported with different refresh-control circuitry, including respective refresh-address counters. Whichever controller has access to a given subset of the DRAM issues refresh requests to the corresponding refresh-address counter. Counters are synchronized before control of a given subset of the DRAM is transferred between controllers to avoid a loss of stored data.

Abstract: Data and error correction information may involve accessing multiple data channels (e.g., 8) and one error detection and correction channel concurrently. This technique requires a total of N+1 row requests for each access, where N is the number of data channels (e.g., 8 data row accesses and 1 error detection and correction row access equals 9 row accesses.) A single (or at least less than N) data channel row may be accessed concurrently with a single error detection and correction row. This reduces the number of row requests to two (2)—one for the data and one for the error detection and correction information. Because, row requests consume power, reducing the number of row requests is more power efficient.

Abstract: A linear encoder may be used to accurately determine a number of cartridges within a magazine. Further, using a set of magnetic sensors within a buffer tube of a firearm, it is possible to determine whether a cartridge is loaded within a chamber of the weapon and/or whether the firearm is jammed. The determination of cartridges within the magazine in conjunction with the determination of whether a cartridge is in a chamber of a firearm can give a user an accurate ammunition count. Further, the use of the linear encoder makes it possible to accurately determine the cartridge count when different cartridges are loaded into the magazine or when the magazine degrades in quality over time. Moreover, the ability for magazines to communicate with a firearm enables a user to determine a total available ammunition to the user in a single display without individually checking each magazine.

Abstract: A stacked processor-plus-memory device includes a processing die with an array of processing elements of an artificial neural network. Each processing element multiplies a first operand—e.g. a weight—by a second operand to produce a partial result to a subsequent processing element. To prepare for these computations, a sequencer loads the weights into the processing elements as a sequence of operands that step through the processing elements, each operand stored in the corresponding processing element. The operands can be sequenced directly from memory to the processing elements or can be stored first in cache. The processing elements include streaming logic that disregards interruptions in the stream of operands.

Abstract: A dynamic random access memory (DRAM) device includes functions configured to aid with operating the DRAM device as part of data caching functions. In response to some write and/or read access commands, the DRAM device is configured to copy a cache line (e.g., dirty cache line) from the main DRAM memory array, place it in a flush buffer, and replace the copied cache line in the main DRAM memory array with a new (e.g., different) cache line of data. In response to conditions and/or events (e.g., explicit command, refresh, write-to-read command sequence, unused data bus bandwidth, full flush buffer, etc.) the DRAM device transmits the cache line from the flush buffer to the controller. The controller may then transmit the cache line to other cache levels.

Abstract: A device includes a memory controller and a cache memory coupled to the memory controller. The cache memory has a first set of cache lines associated with a first memory block and comprising a first plurality of cache storage locations, as well as a second set of cache lines associated with a second memory block and comprising a second plurality of cache storage locations. A first location of the second plurality of cache storage locations comprises cache tag data for both the first set of cache lines and the second set of cache lines.

Abstract: A computer includes a processor and a memory, and the memory stores instructions executable by the processor to receive a first data block from a server remote from the computer and remote from a vehicle; while the computer is installed on board the vehicle, receive a second data block from an electronic control unit (ECU) on the vehicle; compare the first data block and the second data block; upon identifying a match between the first data block and the second data block, replace a stored odometer value on the computer with a first odometer value; and upon identifying a mismatch between the first data block and the second data block, maintain the stored odometer value on the computer. The first data block includes the first odometer value, and the second data block includes a second odometer value.

Abstract: An interconnected stack of one or more Dynamic Random Access Memory (DRAM) die also has one or more custom logic, controller, or processor die. The custom die(s) of the stack include direct channel interfaces that allow direct access to memory regions on one or more DRAMs in the stack. The direct channels are time-division multiplexed such that each DRAM die is associated with a time slot on a direct channel. The custom die configures a first DRAM die to read a block of data and transmit it via the direct channel using a time slot that is assigned to a second DRAM die. The custom die also configures the second memory device to receive the first block of data in its assigned time slot and write the block of data.