Patents by Inventor Michael Raymond

Michael Raymond has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240295961
    Abstract: An integrated circuit (IC) memory device includes an array of storage cells configured into multiple banks. Interface circuitry receives refresh commands from a host memory controller to refresh the multiple banks for a first refresh mode. On-die refresh control circuitry selectively generates local refresh commands to refresh the multiple banks in cooperation with the host memory controller during a designated hidden refresh interval in a second refresh mode. Mode register circuitry stores a value indicating whether the on-die refresh control circuitry is enabled for use during the second refresh mode. The interface circuitry includes backchannel control circuitry to transmit a corrective action control signal during operation in the second refresh mode.
    Type: Application
    Filed: March 7, 2024
    Publication date: September 5, 2024
    Inventors: Michael Raymond Miller, Steven C. Woo, Thomas Vogelsang
  • Publication number: 20240297032
    Abstract: A method of analysing a sample is disclosed in which a solvent emitting capillary is brought into contact with, or proximate to, a sample such that analyte from the sample is absorbed by solvent emitted from the capillary. A voltage is applied to the such that charged droplets of the solvent comprising the analyte from the sample are emitted from the capillary. The charged droplets are caused to be drawn into one or more sampling conduits connected to an atmospheric interface of an analytical instrument.
    Type: Application
    Filed: January 5, 2022
    Publication date: September 5, 2024
    Applicant: Micromass UK Limited
    Inventors: Emrys Jones, Steven Derek Pringle, Michael Raymond Morris
  • Patent number: 12078793
    Abstract: Certain aspects of a firearm sight system that can include a direct view image, an infrared (IR) video image, and/or an auxiliary video image comprising auxiliary information. The firearm scope may be used as s clip-on sight system that transmits the direct view image, the infrared (IR) video image, and the auxiliary video image to a primary firearm scope. The auxiliary video image may include a bore-sighted reticle image superimposed on the direct view image or the IR video image.
    Type: Grant
    Filed: February 13, 2024
    Date of Patent: September 3, 2024
    Assignee: Maztech Industries, LLC
    Inventors: David Michael Masarik, Michael Raymond Masarik, Matthew James Masarik, David Alexander Steinweg
  • Publication number: 20240288239
    Abstract: A linear encoder may be used to accurately determine a number of cartridges within a magazine. Further, using a set of magnetic sensors within a buffer tube of a firearm, it is possible to determine whether a cartridge is loaded within a chamber of the weapon and/or whether the firearm is jammed. The determination of cartridges within the magazine in conjunction with the determination of whether a cartridge is in a chamber of a firearm can give a user an accurate ammunition count. Further, the use of the linear encoder makes it possible to accurately determine the cartridge count when different cartridges are loaded into the magazine or when the magazine degrades in quality over time. Moreover, the ability for magazines to communicate with a firearm enables a user to determine a total available ammunition to the user in a single display without individually checking each magazine.
    Type: Application
    Filed: May 7, 2024
    Publication date: August 29, 2024
    Inventors: David Michael Masarik, Michael Raymond Masarik, Matthew James Masarik
  • Patent number: 12073111
    Abstract: A control component implements pipelined data processing operations in either of two timing domains bridged by a domain-crossing circuit according to one or more configuration signals that indicate relative clock frequencies of the two domain and/or otherwise indicate which of the two timing domains will complete the data processing operations with lowest latency.
    Type: Grant
    Filed: September 8, 2022
    Date of Patent: August 27, 2024
    Assignee: Rambus Inc.
    Inventors: Michael Raymond Miller, Dongyun Lee
  • Patent number: 12072807
    Abstract: Disclosed is a dynamic random access memory that has columns, data rows, tag rows and comparators. Each comparator compares address bits and tag information bits from the tag rows to determine a cache hit and generate address bits to access data information in the DRAM as a multiway set associative cache.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: August 27, 2024
    Assignee: RAMBUS INC.
    Inventors: Thomas Vogelsang, Frederick A. Ware, Michael Raymond Miller, Collins Williams
  • Patent number: 12044080
    Abstract: Systems and methods for hoisting a top drive of a drilling rig. An example system includes a hoisting system having a linear electric motor operable to raise and lower the top drive. An example method includes commencing operation of a processing device to cause operation of the linear electric motor to raise and lower the top drive. The linear electric motor may have a stator connected to and extending vertically along a mast of the drilling rig, and a rotor connected to the top drive and operable to move relative to the stator. The rotor may be connected to the top drive via one or more flexible lines.
    Type: Grant
    Filed: September 15, 2023
    Date of Patent: July 23, 2024
    Assignee: SCHLUMBERGER TECHNOLOGY CORPORATION
    Inventor: Michael Raymond Netecke
  • Publication number: 20240241670
    Abstract: An interconnected stack of one or more Dynamic Random Access Memory (DRAM) die has a base logic die and one or more custom logic or processor die. The processor logic die snoops commands sent to and through the stack. In particular, the processor logic die may snoop mode setting commands (e.g., mode register set—MRS commands). At least one mode setting command that is ignored by the DRAM in the stack is used to communicate a command to the processor logic die. In response the processor logic die may prevent commands, addresses, and data from reaching the DRAM die(s). This enables the processor logic die to send commands/addresses and communicate data with the DRAM die(s). While being able to send commands/addresses and communicate data with the DRAM die(s), the processor logic die may execute software using the DRAM die(s) for program and/or data storage and retrieval.
    Type: Application
    Filed: January 30, 2024
    Publication date: July 18, 2024
    Inventors: Thomas VOGELSANG, Michael Raymond MILLER, Steven C. WOO
  • Publication number: 20240184092
    Abstract: Certain aspects of a firearm sight system that can include a direct view image, an infrared (IR) video image, and/or an auxiliary video image comprising auxiliary information. The firearm scope may be used as s clip-on sight system that transmits the direct view image, the infrared (IR) video image, and the auxiliary video image to a primary firearm scope. The auxiliary video image may include a bore-sighted reticle image superimposed on the direct view image or the IR video image.
    Type: Application
    Filed: February 13, 2024
    Publication date: June 6, 2024
    Inventors: David Michael Masarik, Michael Raymond Masarik, Matthew James Masarik, David Alexander Steinweg, Gregory Philip Petersen
  • Patent number: 12001697
    Abstract: A memory system includes two or more memory controllers capable of accessing the same dynamic, random-access memory (DRAM), one controller having access to the DRAM or a subset of the DRAM at a time. Different subsets of the DRAM are supported with different refresh-control circuitry, including respective refresh-address counters. Whichever controller has access to a given subset of the DRAM issues refresh requests to the corresponding refresh-address counter. Counters are synchronized before control of a given subset of the DRAM is transferred between controllers to avoid a loss of stored data.
    Type: Grant
    Filed: October 15, 2021
    Date of Patent: June 4, 2024
    Assignee: Rambus Inc.
    Inventors: Thomas Vogelsang, Steven C. Woo, Michael Raymond Miller
  • Patent number: 12001283
    Abstract: Data and error correction information may involve accessing multiple data channels (e.g., 8) and one error detection and correction channel concurrently. This technique requires a total of N+1 row requests for each access, where N is the number of data channels (e.g., 8 data row accesses and 1 error detection and correction row access equals 9 row accesses.) A single (or at least less than N) data channel row may be accessed concurrently with a single error detection and correction row. This reduces the number of row requests to two (2)—one for the data and one for the error detection and correction information. Because, row requests consume power, reducing the number of row requests is more power efficient.
    Type: Grant
    Filed: April 4, 2023
    Date of Patent: June 4, 2024
    Assignee: Rambus Inc.
    Inventors: Michael Raymond Miller, Stephen Magee, John Eric Linstadt
  • Patent number: 11990647
    Abstract: A modular battery system includes an array of battery modules arranged in at least one stack. Each battery module includes a plurality of battery cells, a first side having positive and negative receptacles and a second side, that is opposite of the first side, having positive and negative plugs. The receptacles and plugs are configured such that adjacent battery modules in a side-by-side relationship are electrically coupled together via plug and receptacle connections and such that the battery modules are electrically coupled together in parallel. An interconnection electrically couples each stack of battery modules together via plug and receptacle connections with one of the battery modules in each stack such that the stacks of battery modules are electrically coupled together in parallel. Each of the battery modules includes a thermal conditioning system configured to thermally isolate the battery module from the other battery modules.
    Type: Grant
    Filed: June 6, 2023
    Date of Patent: May 21, 2024
    Assignee: Textron Innovations Inc.
    Inventors: Michael Raymond Hull, Steven Loveland, Yue Fan
  • Publication number: 20240157599
    Abstract: Stone slabs, and systems and methods of forming slabs, are described. Some example slabs include a pattern defined by a particulate mineral mix. The pattern includes one or more characteristics that differ from other regions of the slab where the pattern is not present.
    Type: Application
    Filed: November 15, 2023
    Publication date: May 16, 2024
    Inventors: Jon Louis Grzeskowiak, II, Martin E. Davis, Michael Raymond Mead
  • Publication number: 20240161479
    Abstract: Methods and systems directed to processing of a polarized image are disclosed. A method may involve determining a polarization characterization for a polarized image. The polarization characterization is indicative of polarization data associated with a plurality of polarization directions of incident light in the polarized image. The method may also involve extracting, from the polarized image, a first collection of global features and a second collection of local features. The method may further involve performing, based on the polarization characterization, a global feature fusion to fuse global features in the first collection, and a local feature fusion to fuse local features in the second collection. The method may involve compositing the polarization characterization with the fused global features and the fused local features to generate a reconstructed image. The method may also involve providing the reconstructed image to an image processing resource to perform one or more image processing tasks.
    Type: Application
    Filed: March 21, 2022
    Publication date: May 16, 2024
    Inventors: Jenn-Kwei Tyan, Michael Raymond Piacentino
  • Publication number: 20240153548
    Abstract: Disclosed is a memory system including a memory component having at least one tag row and at least one data row and multiple ways to hold a data group as a cache-line or cache-block. The memory system includes a memory controller that is connectable to the memory component to implement a cache and operable with the memory controller and the memory component in each of a plurality of operating modes including a first and second operating mode having differing addressing and timing requirements for accessing the data group. The first operating mode having placement of each of at least two ways of a data group in differing rows in the memory component, with tag access and data access not overlapped. The second operating mode having placement of all ways of a data group in a same row in the memory component, with tag access and data access overlapped.
    Type: Application
    Filed: November 6, 2023
    Publication date: May 9, 2024
    Inventors: Frederick A. Ware, Thomas Vogelsang, Michael Raymond Miller, Collins Williams
  • Publication number: 20240128071
    Abstract: An apparatus is disclosed comprising a first device for generating aerosol, smoke or vapour from one or more regions of a target, an inlet conduit to an ion analyser or mass spectrometer, the inlet conduit having an inlet through which the aerosol, smoke or vapour passes, and a Venturi pump arrangement arranged and adapted to direct the aerosol, smoke or vapour towards the inlet.
    Type: Application
    Filed: October 20, 2023
    Publication date: April 18, 2024
    Inventors: Zoltán TAKÁTS, Júlia BALOG, Steven Derek PRINGLE, Tamás KARANCSI, Michael Raymond MORRIS, Lajos GÖDÖRHÁZY, Dániel SZALAY, Dániel SIMON
  • Patent number: 11959823
    Abstract: Apparatus and methods for measuring backlash of a drive train of an equipment unit. The drive train may comprise an input member operatively connected with an actuator and an output member operatively connected with a work portion of the equipment unit. An example apparatus may include a sensor operable to facilitate operational measurements indicative of an operational parameter associated with the drive train, and a processing device operable to cause the actuator to move the input member until the output member moves, record the operational measurements while the actuator moves the input member, and determine a backlash of the drive train by determining a difference between the operational measurements when the input member starts to move and the operational measurements when the output member starts to move.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: April 16, 2024
    Assignee: SCHLUMBERGER TECHNOLOGY CORPORATION
    Inventors: Alejandro Camacho Cardenas, Michael Raymond Netecke
  • Patent number: 11960438
    Abstract: A stacked processor-plus-memory device includes a processing die with an array of processing elements of an artificial neural network. Each processing element multiplies a first operand—e.g. a weight—by a second operand to produce a partial result to a subsequent processing element. To prepare for these computations, a sequencer loads the weights into the processing elements as a sequence of operands that step through the processing elements, each operand stored in the corresponding processing element. The operands can be sequenced directly from memory to the processing elements or can be stored first in cache. The processing elements include streaming logic that disregards interruptions in the stream of operands.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: April 16, 2024
    Assignee: Rambus Inc.
    Inventors: Steven C. Woo, Michael Raymond Miller
  • Publication number: 20240119989
    Abstract: Row hammer is mitigated by issuing, to a memory device, mitigation operation (MOP) commands in order to cause the refresh of rows at a specified vicinity of a suspected aggressor row. These mitigation operation commands are each associated with respective row addresses that indicate the suspected aggressor row and an indicator of which neighbor row in the vicinity of the suspected aggressor row is to be refreshed. The mitigation operation commands are issued in response to a fixed number of activate commands. The suspected aggressor row is selected by randomly choosing, with equal probability, one of the N previous activate commands to supply its associated row address as the suspected aggressor row address. The neighbor row may be selected randomly with a probability that diminishes inversely with the distance between the suspected aggressor row and the neighbor row.
    Type: Application
    Filed: October 2, 2023
    Publication date: April 11, 2024
    Inventors: Steven C. WOO, Michael Raymond MILLER
  • Patent number: 11934654
    Abstract: An integrated circuit (IC) memory device includes an array of storage cells configured into multiple banks. Interface circuitry receives refresh commands from a host memory controller to refresh the multiple banks for a first refresh mode. On-die refresh control circuitry selectively generates local refresh commands to refresh the multiple banks in cooperation with the host memory controller during a designated hidden refresh interval in a second refresh mode. Mode register circuitry stores a value indicating whether the on-die refresh control circuitry is enabled for use during the second refresh mode. The interface circuitry includes backchannel control circuitry to transmit a corrective action control signal during operation in the second refresh mode.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: March 19, 2024
    Assignee: Rambus Inc.
    Inventors: Michael Raymond Miller, Steven C. Woo, Thomas Vogelsang