Abstract: A system is provided for unified management of power, performance, and thermals in computer systems. This system incorporates elements to effectively address all aspects of managing computing systems in an integrated manner, instead of independently. The system employs an infrastructure for real-time measurements feedback, an infrastructure for regulating system activity, component operating levels, and environmental control, a dedicated control structure for guaranteed response/preemptive action, and interaction and integration components. The system provides interfaces for user-level interaction. The system also employs methods to address power/thermal concerns at multiple timescales. In addition, the system improves efficiency by adopting an integrated approach, rather than treating different aspects of the power/thermal problem as individual issues to be addressed in a piecemeal fashion.

Abstract: A system for identifying a subset of sensors to sample to reduce the frequency of sensor access. The system determines rise times and records values for the sensors in the system. A time criticality of the sensors is determined based on the rise times. The system processes the sensors by first creating sensor subsets based on one or more constraints on the sensors. The system monitors the values of the sensors in a sensor subset and flags a sensor when it makes a determination that, prior to a next scheduled sampling of the sensor subset, the value of a sensor in the monitored sensor subset will exceed a threshold constraint. The system moves those flagged sensors to a second sensor subset which complies with the sensor's constraints.

Abstract: A weighted event counting system and method for processor performance measurements provides low latency and low error performance measurement capability. A weighted performance counter accumulates a performance count according to a plurality of event signals provided from functional units in the processor. Differing weights are applied to the event signals in according to the correlation between each event with processor performance. The weights may be provided from programmable registers, so that the weights can be adjusted under program control. The event signals may be combined to reduce the bit-width of the set of event signal, with mutually-exclusive events merged in single fields of the combinatorial result and events having the same weights merged according to a sub-total. The weights are applied to the combinatorial result and used to update a performance count. The performance count can then be used by power management software or hardware to make adjustments in operating parameters of the processor.

Abstract: A circuit for dynamically monitoring the operation of an integrated circuit under differing temperature, frequency, and voltage (including localized noise and droop), and for detecting early life wear-out mechanisms (e.g., NBTI, hot electrons).

Abstract: The present invention thus provides for a method, system, and computer-usable medium that afford an equitably charging of a customer for computer usage time. In a preferred embodiment, the method includes the steps of: tracking an amount of computer resources in a Simultaneous Multithreading (SMT) computer that are available to a customer for a specified period of time; determining if the computer resources in the SMT computer are operating at a nominal rate; and in response to determining that the computer resources are operating at a non-nominal rate, adjusting a billing charge to the customer, wherein the billing charge reflects that the customer has available computer resources, in the SMT computer, that are not operating at the nominal rate during the specified period of time.

Abstract: A weighted event counting system and method for processor performance measurements provides low latency and low error performance measurement capability. A weighted performance counter accumulates a performance count according to a plurality of event signals provided from functional units in the processor. Differing weights are applied to the event signals in according to the correlation between each event with processor performance. The weights may be provided from programmable registers, so that the weights can be adjusted under program control. The event signals may be combined to reduce the bit-width of the set of event signal, with mutually-exclusive events merged in single fields of the combinatorial result and events having the same weights merged according to a sub-total. The weights are applied to the combinatorial result and used to update a performance count. The performance count can then be used by power management software or hardware to make adjustments in operating parameters of the processor.

Abstract: A processor core for transitioning a debugging unit between a plurality of operating states generates trace data as it processes operating signals of an instruction stream. The processor core provides a trigger event signal to the debugging unit in response to a trigger instruction signal within the instruction stream that is representative of triggering instruction for transitions debugging unit to one of (1) a base operating state, (2) a dynamic storage operating state or (3) a static storage operating state. Concurrently or alternatively, the processor core can provide the trigger event signal to the debugging unit as a function of generated trigger data in response to additional operational instructions within the instruction stream.

Abstract: A processor core for transitioning a debugging unit between a plurality of operating states in response to an instruction stream is disclosed. The processor core generates trace data as it processes operating signals of the instruction stream. The processor core provides a first trigger event signal to the debugging unit in response to a first trigger instruction signal within the instruction stream that is representative of a triggering instruction to transitions the debugging unit to a base operating state. The processor core provides a second trigger event signal to the debugging unit in response to a second trigger instruction signal within the instruction stream that is representative of a triggering instruction to dynamically store trace data within the memory component of the debugging unit.