Patents by Inventor Michael S. Mazzola

Michael S. Mazzola has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7978483
    Abstract: Components, systems and methods for generating variable frequency AC voltage from a DC power supply are described. The components include a full-bridge (FB) parallel load resonant (PLR) converter which operates in discontinuous conduction mode. The PLR converter includes MOSFETs in an H-bridge configuration and employs a topology which minimizes inductance. The PLR converter can be coupled to a single or poly-phase bridge for use as an inverter. The inverter can be used to produce an AC sinusoidal waveform from a low voltage, high current DC power supply. Systems and techniques for modulating the output from the PLR converter to produce an AC sinusoidal waveform having desired characteristics, including frequency and voltage, are also provided. The PLR converter can also be coupled to a rectifier for use as a DC-DC converter.
    Type: Grant
    Filed: January 13, 2009
    Date of Patent: July 12, 2011
    Assignee: Mississippi State University
    Inventors: Michael S. Mazzola, James R. Gafford
  • Publication number: 20110121884
    Abstract: A method for rendering a half-bridge circuit containing normally on switches such as junction field effect transistors (JFETs) inherently safe from uncontrolled current flow is described. The switches can be made from silicon carbide or from silicon. The methods described herein allow for the use of better performing normally on switches in place of normally off switches in integrated power modules thereby improving the efficiency, size, weight, and cost of the integrated power modules. As described herein, a power supply can be added to the gate driver circuitry. The power supply can be self starting and self oscillating while being capable of deriving all of its source energy from the terminals supplying electrical potential to the normally on switch through the gate driver. The terminal characteristics of the normally on switch can then be coordinated to the input-to-output characteristics of the power supply.
    Type: Application
    Filed: February 4, 2011
    Publication date: May 26, 2011
    Applicant: SEMISOUTH LABORATORIES, INC.
    Inventors: Michael S. MAZZOLA, Robin L. KELLEY
  • Patent number: 7907001
    Abstract: A method for rendering a half-bridge circuit containing normally on switches such as junction field effect transistors (JFETs) inherently safe from uncontrolled current flow is described. The switches can be made from silicon carbide or from silicon. The methods described herein allow for the use of better performing normally on switches in place of normally off switches in integrated power modules thereby improving the efficiency, size, weight, and cost of the integrated power modules. As described herein, a power supply can be added to the gate driver circuitry. The power supply can be self starting and self oscillating while being capable of deriving all of its source energy from the terminals supplying electrical potential to the normally on switch through the gate driver. The terminal characteristics of the normally on switch can then be coordinated to the input-to-output characteristics of the power supply.
    Type: Grant
    Filed: September 10, 2009
    Date of Patent: March 15, 2011
    Assignee: SemiSouth Laboratories, Inc.
    Inventors: Michael S. Mazzola, Robin Kelley
  • Publication number: 20110003456
    Abstract: A method of making a semi-insulating epitaxial layer includes implanting a substrate or a first epitaxial layer formed on the substrate with boron ions to form a boron implanted region on a surface of the substrate or on a surface of the first epitaxial layer, and growing a second epitaxial layer on the boron implanted region of the substrate or on the boron implanted region of the first epitaxial layer to form a semi-insulating epitaxial layer.
    Type: Application
    Filed: September 14, 2010
    Publication date: January 6, 2011
    Applicant: SEMISOUTH LABORATORIES, INC.
    Inventor: Michael S. MAZZOLA
  • Patent number: 7821015
    Abstract: A method of making a semi-insulating epitaxial layer includes implanting a substrate or a first epitaxial layer formed on the substrate with boron ions to form a boron implanted region on a surface of the substrate or on a surface of the first epitaxial layer, and growing a second epitaxial layer on the boron implanted region of the substrate or on the boron implanted region of the first epitaxial layer to form a semi-insulating epitaxial layer.
    Type: Grant
    Filed: June 18, 2007
    Date of Patent: October 26, 2010
    Assignee: SemiSouth Laboratories, Inc.
    Inventor: Michael S. Mazzola
  • Publication number: 20100026370
    Abstract: A method for rendering a half-bridge circuit containing normally on switches such as junction field effect transistors (JFETS) inherently safe from uncontrolled current flow is described. The switches can be made from silicon carbide or from silicon. The methods described herein allow for the use of better performing normally on switches in place of normally off switches in integrated power modules thereby improving the efficiency, size, weight, and cost of the integrated power modules. As described herein, a power supply can be added to the gate driver circuitry. The power supply can be self starting and self oscillating while being capable of deriving all of its source energy from the terminals supplying electrical potential to the normally on switch through the gate driver. The terminal characteristics of the normally on switch can then be coordinated to the input-to-output characteristics of the power supply.
    Type: Application
    Filed: September 10, 2009
    Publication date: February 4, 2010
    Applicant: SEMISOUTH LABORATORIES, INC.
    Inventors: Michael S. Mazzola, Robin L. Kelley
  • Publication number: 20100020581
    Abstract: Components, systems and methods for generating variable frequency AC voltage from a DC power supply are described. The components include a fullbridge (FB) parallel load resonant (PLR) converter which operates in discontinuous conduction mode. The PLR converter includes MOSFETs in an H-bridge configuration and employs a topology which minimizes inductance. The PLR converter can be coupled to a single or poly-phase bridge for use as an inverter. The inverter can be used to produce an AC sinusoidal waveform from a low voltage, high current DC power supply. Systems and techniques for modulating the output from the PLR converter to produce an AC sinusoidal waveform having desired characteristics, including frequency and voltage, are also provided. The PLR converter can also be coupled to a rectifier for use as a DC-DC converter.
    Type: Application
    Filed: January 13, 2009
    Publication date: January 28, 2010
    Applicant: MISSISSIPPI STATE UNIVERSITY
    Inventors: Michael S. Mazzola, James R. Gafford
  • Patent number: 7638379
    Abstract: Semiconductor devices and methods of making the devices are described. The devices can be implemented in SiC and can include epitaxially grown n-type drift and p-type trenched gate regions, and an n-type epitaxially regrown channel region on top of the trenched p-gate regions. A source region can be epitaxially regrown on top of the channel region or selectively implanted into the channel region. Ohmic contacts to the source, gate and drain regions can then be formed. The devices can include edge termination structures such as guard rings, junction termination extensions (JTE), or other suitable p-n blocking structures. The devices can be fabricated with different threshold voltages, and can be implemented for both depletion and enhanced modes of operation for the same channel doping. The devices can be used as discrete power transistors and in digital, analog, and monolithic microwave integrated circuits.
    Type: Grant
    Filed: November 6, 2007
    Date of Patent: December 29, 2009
    Assignees: SemiSouth Laboratories, Inc., Mississippi State University
    Inventors: Lin Cheng, Michael S. Mazzola
  • Patent number: 7602228
    Abstract: A method for rendering a half-bridge circuit containing normally on switches such as junction field effect transistors (JFETs) inherently safe from uncontrolled current flow is described. The switches can be made from silicon carbide or from silicon. The methods described herein allow for the use of better performing normally on switches in place of normally off switches in integrated power modules thereby improving the efficiency, size, weight, and cost of the integrated power modules. As described herein, a power supply can be added to the gate driver circuitry. The power supply can be self starting and self oscillating while being capable of deriving all of its source energy from the terminals supplying electrical potential to the normally on switch through the gate driver. The terminal characteristics of the normally on switch can then be coordinated to the input-to-output characteristics of the power supply.
    Type: Grant
    Filed: May 22, 2007
    Date of Patent: October 13, 2009
    Assignee: SemiSouth Laboratories, Inc.
    Inventors: Michael S. Mazzola, Robin L. Kelley
  • Patent number: 7499290
    Abstract: Components, systems and methods for generating variable frequency AC voltage from a DC power supply are described. The components include a full-bridge (FB) parallel load resonant (PLR) converter which operates in discontinuous conduction mode. The PLR converter includes MOSFETs in an H-bridge configuration and employs a topology which minimizes inductance. The PLR converter can be coupled to a single or poly-phase bridge for use as an inverter. The inverter can be used to produce an AC sinusoidal waveform from a low voltage, high current DC power supply. Systems and techniques for modulating the output from the PLR converter to produce an AC sinusoidal waveform having desired characteristics, including frequency and voltage, are also provided. The PLR converter can also be coupled to a rectifier for use as a DC-DC converter.
    Type: Grant
    Filed: May 19, 2005
    Date of Patent: March 3, 2009
    Assignee: Mississippi State University
    Inventors: Michael S. Mazzola, James R. Gafford
  • Publication number: 20080290927
    Abstract: A method for rendering a half-bridge circuit containing normally on switches such as junction field effect transistors (JFETS) inherently safe from uncontrolled current flow is described. The switches can be made from silicon carbide or from silicon. The methods described herein allow for the use of better performing normally on switches in place of normally off switches in integrated power modules thereby improving the efficiency, size, weight, and cost of the integrated power modules. As described herein, a power supply can be added to the gate driver circuitry. The power supply can be self starting and self oscillating while being capable of deriving all of its source energy from the terminals supplying electrical potential to the normally on switch through the gate driver. The terminal characteristics of the normally on switch can then be coordinated to the input-to-output characteristics of the power supply.
    Type: Application
    Filed: May 22, 2007
    Publication date: November 27, 2008
    Inventors: Michael S. Mazzola, Robin L. Kelley
  • Publication number: 20080251793
    Abstract: A junction barrier Schottky (JBS) rectifier device and a method of making the device are described. The device comprises an epitaxially grown first n-type drift layer and p-type regions forming p+-n junctions and self-planarizing epitaxially over-grown second n-type drift regions between and, optionally, on top of the p-type regions. The device may include an edge termination structure such as an exposed or buried P+ guard ring, a regrown or implanted junction termination extension (JTE) region, or a “deep” mesa etched down to the substrate. The Schottky contact to the second n-type drift region and the ohmic contact to the p-type region together serve as an anode. The cathode can be formed by ohmic contact to the n-type region on the backside of the wafer. The devices can be used in monolithic digital, analog, and microwave integrated circuits.
    Type: Application
    Filed: June 26, 2008
    Publication date: October 16, 2008
    Applicant: SemiSouth Laboratories, Inc.
    Inventors: Michael S. MAZZOLA, Lin CHENG
  • Patent number: 7416929
    Abstract: A switching element combining a self-aligned, vertical junction field effect transistor with etched-implanted gate and an integrated antiparallel Schottky barrier diode is described. The anode of the diode is connected to the source of the transistor at the device level in order to reduce losses due to stray inductances. The SiC surface in the SBD anode region is conditioned through dry etching to achieve a low Schottky barrier height so as to reduce power losses associated with the turn on voltage of the SBD.
    Type: Grant
    Filed: June 12, 2007
    Date of Patent: August 26, 2008
    Assignees: SemiSouth Laboratories, Inc., Mississippi State University
    Inventors: Michael S. Mazzola, Joseph N. Merrett
  • Publication number: 20080124853
    Abstract: Semiconductor devices and methods of making the devices are described. The devices can be implemented in SiC and can include epitaxially grown n-type drift and p-type trenched gate regions, and an n-type epitaxially regrown channel region on top of the trenched p-gate regions. A source region can be epitaxially regrown on top of the channel region or selectively implanted into the channel region. Ohmic contacts to the source, gate and drain regions can then be formed. The devices can include edge termination structures such as guard rings, junction termination extensions (JTE), or other suitable p-n blocking structures. The devices can be fabricated with different threshold voltages, and can be implemented for both depletion and enhanced modes of operation for the same channel doping. The devices can be used as discrete power transistors and in digital, analog, and monolithic microwave integrated circuits.
    Type: Application
    Filed: November 6, 2007
    Publication date: May 29, 2008
    Applicants: SEMISOUTH LABORATORIES, INC., MISSISSIPPI STATE UNIVERSITY
    Inventors: Lin Cheng, Michael S. Mazzola
  • Publication number: 20070290212
    Abstract: A method of making a semi-insulating epitaxial layer includes implanting a substrate or a first epitaxial layer formed on the substrate with boron ions to form a boron implanted region on a surface of the substrate or on a surface of the first epitaxial layer, and growing a second epitaxial layer on the boron implanted region of the substrate or on the boron implanted region of the first epitaxial layer to form a semi-insulating epitaxial layer.
    Type: Application
    Filed: June 18, 2007
    Publication date: December 20, 2007
    Inventor: Michael S. Mazzola
  • Publication number: 20070292074
    Abstract: An optically active material is used to create power devices and circuits having significant performance advantages over conventional methods for affecting optical control of power electronics devices and circuits. A silicon-carbide optically active material is formed by compensating shallow donors with the boron related D-center. The resulting material can be n-type or p-type but it is distinguished from other materials by the ability to induce persistent photoconductivity in it when illuminated by electromagnetic radiation with a photon energy in excess of the threshold energy required to photoexcite electrons from the D-center to allowed states close to the conduction band edge, which varies from polytype to polytype.
    Type: Application
    Filed: June 18, 2007
    Publication date: December 20, 2007
    Inventor: Michael S. Mazzola
  • Patent number: 7294860
    Abstract: A switching element combining a self-aligned, vertical junction field effect transistor with etched-implanted gate and an integrated antiparallel Schottky barrier diode is described. The anode of the diode is connected to the source of the transistor at the device level in order to reduce losses due to stray inductances. The SiC surface in the SBD anode region is conditioned through dry etching to achieve a low Schottky barrier height so as to reduce power losses associated with the turn on voltage of the SBD.
    Type: Grant
    Filed: July 8, 2005
    Date of Patent: November 13, 2007
    Assignees: Mississippi State University, SemiSouth Laboratories, Inc.
    Inventors: Michael S. Mazzola, Joseph N. Merrett
  • Patent number: 6767783
    Abstract: A method of making vertical diodes and transistors in SiC is provided. The method according to the invention uses a mask (e.g., a mask that has been previously used for etching features into the device) for selective epitaxial growth or selective ion implantation. In this manner, the gate and base regions of static induction transistors and bipolar junction transistors can be formed in a self-aligned process. A method of making planar diodes and planar edge termination structures (e.g., guard rings) is also provided.
    Type: Grant
    Filed: July 12, 2002
    Date of Patent: July 27, 2004
    Assignee: Mississippi State University-Research and Technology Corporation (RTC)
    Inventors: Jeffrey B. Casady, Geoffrey E. Carter, Yaroslav Koshka, Michael S. Mazzola, Igor Sankin
  • Publication number: 20030034495
    Abstract: A method of making vertical diodes and transistors in SiC is provided. The method according to the invention uses a mask (e.g., a mask that has been previously used for etching features into the device) for selective epitaxial growth or selective ion implantation. In this manner, the gate and base regions of static induction transistors and bipolar junction transistors can be formed in a self-aligned process. A method of making planar diodes and planar edge termination structures (e.g., guard rings) is also provided.
    Type: Application
    Filed: July 12, 2002
    Publication date: February 20, 2003
    Inventors: Jeffrey B. Casady, Geoffrey E. Carter, Yaroslav Koshka, Michael S. Mazzola, Igor Sankin
  • Patent number: 6503782
    Abstract: A method and device produced for design, construction, and use of integrated circuits in wide bandgap semiconductors, including methods for fabrication of n-channel and p-channel junction field effect transistors on a single wafer or die, such that the produced devices may have pinchoff voltages of either positive or negative polarities. A first layer of either p-type or n-type is formed as a base. An alternating, channel layer of either n-type or p-type is then formed, followed by another layer of the same type as the first layer. Etching is used to provide contacts for the gates, source, and drain of the device. In one variation, pinchoff voltage is controlled via dopant level and thickness the channel region. In another variation, pinchoff voltage is controlled by variation of dopant level across the channel layer; and in another variation, pinchoff voltage is controlled by both thickness and variation of dopant level.
    Type: Grant
    Filed: March 2, 2001
    Date of Patent: January 7, 2003
    Assignee: Mississippi State University Research and Technology Corporation (RTC)
    Inventors: Jeffrey Blaine Casady, Benjamin Blalock, Stephen E. Saddow, Michael S. Mazzola