Abstract: A method and device produced for design, construction, and use of integrated circuits in wide bandgap semiconductors, including methods for fabrication of n-channel and p-channel junction field effect transistors on a single wafer or die, such that the produced devices may have pinchoff voltages of either positive or negative polarities. A first layer of either p-type or n-type is formed as a base. An alternating, channel layer of either n-type or p-type is then formed, followed by another layer of the same type as the first layer. Etching is used to provide contacts for the gates, source, and drain of the device. In one variation, pinchoff voltage is controlled via dopant level and thickness the channel region. In another variation, pinchoff voltage is controlled by variation of dopant level across the channel layer; and in another variation, pinchoff voltage is controlled by both thickness and variation of dopant level.

Abstract: Devices and methods for fabricating wholly silicon carbide heterojunction bipolar transistors (HBTs) using germanium base doping to produce suitable emitter/base heterojunctions. In one variation, all device layers are are grown epitaxially and the heterojunction is created by introducing a pseudoalloying material, such as germanium, to form a graded implant. In other variations, the device epitaxial layers are 1) grown directly onto a semi-insulating substrate, 2) the semi-insulating epitaxial layer is grown onto a conducting substrate; 3) the subcollector is grown on a lightly doped p-type epitaxial layer grown on a conducting substrate; and 4) the subcollector is grown directly on a conducting substrate. Another variation comprises a multi-finger HBT with bridging conductor connections among emitter fingers. Yet another variation includes growth of layers using dopants other than nitrogent or aluminum.

Abstract: Devices and methods for fabricating wholly silicon carbide heterojunction bipolar transistors (HBTs) using germanium base doping to produce suitable emitter/base heterojunctions. In one variation, all device layers are are grown epitaxially and the heterojunction is created by introducing a pseudoalloying material, such as germanium, to form a graded implant. In other variations, the device epitaxial layers are 1) grown directly onto a semi-insulating substrate, 2) the semi-insulating epitaxial layer is grown onto a conducting substrate; 3) the subcollector is grown on a lightly doped p-type epitaxial layer grown on a conducting substrate; and 4) the subcollector is grown directly on a conducting substrate. Another variation comprises a multi-finger HBT with bridging conductor connections among emitter fingers. Yet another variation includes growth of layers using dopants other than nitrogent or aluminum.

Abstract: Acoustical shock waves are generated by electrical sparks within a gap between electrodes adjustably positioned for exposure to water adjacent a surface immersed therein. High voltage electrical energy derived from a constant current power supply, is stored in a capacitor for rapid. application to the electrodes by discharge during cyclic periods of short duration under remote control in order to render the acoustical shock waves so generated effective in preventing biofouling of the surface by organisms in the water.

Abstract: Semi-insulating gallium arsenide wafers manufactured with varying silicon nsity shallow donors are copper compensated by heating to temperature of at least 550.degree. C. to thermally diffuse the copper into the wafers and thereby provide deep copper acceptors in the wafer. Higher annealing temperatures are employed for higher concentrations of silicon in the wafers and the thermal diffusion is accomplished in the presence of copper, and in some instances, in the presence of varying quantities of arsenic. The copper compensated, silicon doped, gallium arsenide wafers obtained have the electrical property characteristic capability of being used as photoconductive switching components. In one aspect of the invention the silicon doped gallium arsenide wafer is sealed in a quartz ampoule in the presence of solid copper and solid arsenic and heated to the annealing temperature.