Abstract: A memory array having at least two memory cells accessed for each row address to retain a sufficient electric charge to properly store “1” and “0” bits. For such a memory array both even and odd row decoders in the array are permanently enabled so that each row address the array receives causes the even row decoder to energize at least one even word line and the odd row decoder to energize at least one odd word line. As a result, at least two memory cells are accessed for each row address so that each “1” or “0” bit is stored as an electric charge in at least two memory cells. By grouping enough memory cells together in this manner to store each “1” and “0” bit, the grouped memory cells are able to retain a sufficient total electric charge as a group to properly store each bit even when individual memory cells in the group are unable to do so.

Abstract: A system is disclosed for controlling the tension in rod or bar products being rolled continuously in first and second roll stands independently driven by drive motors. A first surface velocity gauge is positioned at the delivery side of the first roll stand and a second surface velocity gauge is positioned at the entry side of the second roll stand. The first and second gauges are operative, respectively, to continuously measure and generate control signals representative of the exit surface velocity of the product exiting the first roll stand and the entry surface velocity of the product entering the second roll stand. Separately operable controllers are provided for varying the operating speeds of the roll stand drive motors.

Abstract: In a single strand hot rolling mill finishing section a plurality of multi-stand prefinishing rolling units are arranged along and are selectively shiftable onto and off of a first pass line segment. A multi-stand finishing rolling unit and a multi-stand post finishing rolling unit are arranged sequentially along a second pass line segment. A switch and associated delivery guides are selectively operable to direct products from the first pass line segment to the second pass line segment either at a location upstream of said finishing rolling unit, or alternatively, at a location between the finishing rolling unit and the post finishing rolling unit. With this arrangement, final rolling in the post finishing rolling unit may be preceded with or without rolling in the finishing rolling unit and with or without rolling in one or more of the prefinishing rolling units.

Abstract: Operation control circuitry for altering a sequence of internal memory operations in a memory device while in a test mode. The operation control circuitry includes a code circuit for providing an operation code in accordance to a user programmable code. An operation control circuit generates operation control signals in response to receiving command signals from a command circuit included in the operation control circuitry. The operation control signals generated by the operation control circuit control the occurrence of the internal memory operations according to an operation code.

Abstract: The present invention provides a method and apparatus for training a person to learn a cognitive/functional task that requires a sequence of decisions and a corresponding sequence of actions. According to a preferred embodiment of the invention, a cognitive/functional task is decomposed into critical elements and non-critical elements. The critical elements have distinguishing features and are essential to the cognitive/functional task. The critical and non-critical elements are presented to a trainee in a predetermined sequence in a simulated environment through, for example, a virtual reality device. The trainee is trained to act in accordance with the critical and non-critical elements presented. Furthermore, a data processing system is used to monitor the actions taken by the trainee in the simulated environment in response to the presented critical and non-critical elements. Moreover, the learning receptivity and learning achievement by the trainee is measured via a brain wave detection device.

Abstract: A dual mode, full density/half density SDRAM includes a refresh controller specifically adapted to refresh memory cells of the SDRAM in the half density mode at a rate that is significantly slower than the rate at which the memory cells are refreshed in the full density mode. In the full density mode, the refresh controller increments a counter at a rate that is half the rate the counter is incremented in the full density mode. A refresh trigger pulse, which initiates the refresh of the memory cells, is generated when the counter has incremented to one of a first counter stage in the full density mode and a counter stage two stages beyond the first counter stage in the half density mode. Circuitry is also provided for ignoring some auto-refresh commands applied to the SDRAM in the half density mode so that the memory cells are also refreshed less frequently in the auto-refresh mode.

Abstract: A dual mode, full density/half density SDRAM includes a refresh controller specifically adapted to refresh memory cells of the SDRAM in the half density mode at a rate that is significantly slower than the rate at which the memory cells are refreshed in the full density mode. In the full density mode, the refresh controller increments a counter at a rate that is half the rate the counter is incremented in the full density mode. A refresh trigger pulse, which initiates the refresh of the memory cells, is generated when the counter has incremented to one of a first counter stage in the full density mode and a counter stage two stages beyond the first counter stage in the half density mode. Circuitry is also provided for ignoring some auto-refresh commands applied to the SDRAM in the half density mode so that the memory cells are also refreshed less frequently in the auto-refresh mode.

Abstract: A dual mode, full density/half density SDRAM includes a refresh controller specifically adapted to refresh memory cells of the SDRAM in the half density mode at a rate that is significantly slower than the rate at which the memory cells are refreshed in the full density mode. In the full density mode, the refresh controller increments a counter at a rate that is half the rate the counter is incremented in the full density mode. A refresh trigger pulse, which initiates the refresh of the memory cells, is generated when the counter has incremented to one of a first counter stage in the full density mode and a counter stage two stages beyond the first counter stage in the half density mode. Circuitry is also provided for ignoring some auto-refresh commands applied to the SDRAM in the half density mode so that the memory cells are also refreshed less frequently in the auto-refresh mode.

Abstract: A dual mode, full density/half density SDRAM includes a refresh controller specifically adapted to refresh memory cells of the SDRAM in the half density mode at a rate that is significantly slower than the rate at which the memory cells are refreshed in the full density mode. In the full density mode, the refresh controller increments a counter at a rate that is half the rate the counter is incremented in the full density mode. A refresh trigger pulse, which initiates the refresh of the memory cells, is generated when the counter has incremented to one of a first counter stage in the full density mode and a counter stage two stages beyond the first counter stage in the half density mode. Circuitry is also provided for ignoring some auto-refresh commands applied to the SDRAM in the half density mode so that the memory cells are also refreshed less frequently in the auto-refresh mode.

Abstract: A dual mode, full density/half density SDRAM includes a refresh controller specifically adapted to refresh memory cells of the SDRAM in the half density mode at a rate that is significantly slower than the rate at which the memory cells are refreshed in the full density mode. In the full density mode, the refresh controller increments a counter at a rate that is half the rate the counter is incremented in the full density mode. A refresh trigger pulse, which initiates the refresh of the memory cells, is generated when the counter has incremented to one of a first counter stage in the full density mode and a counter stage two stages beyond the first counter stage in the half density mode. Circuitry is also provided for ignoring some auto-refresh commands applied to the SDRAM in the half density mode so that the memory cells are also refreshed less frequently in the auto-refresh mode.

Abstract: A dual mode, full density/half density SDRAM includes a refresh controller specifically adapted to refresh memory cells of the SDRAM in the half density mode at a rate that is significantly slower than the rate at which the memory cells are refreshed in the full density mode. In the full density mode, the refresh controller increments a counter at a rate that is half the rate the counter is incremented in the full density mode. A refresh trigger pulse, which initiates the refresh of the memory cells, is generated when the counter has incremented to one of a first counter stage in the full density mode and a counter stage two stages beyond the first counter stage in the half density mode. Circuitry is also provided for ignoring some auto-refresh commands applied to the SDRAM in the half density mode so that the memory cells are also refreshed less frequently in the auto-refresh mode.

Abstract: A DRAM array is repairable when the array includes memory cells that are defective because their storage capacitors are unable to retain a sufficient electric charge to properly store “1” and “0” bits. To repair the array, both even and odd row decoders in the array are permanently enabled so that each row address the array receives causes the even row decoder to energize at least one even word line and the odd row decoder to energize at least one odd word line. As a result, at least two memory cells are accessed for each row address so that each “1” or “0” bit is stored as an electric charge in at least two memory cells. By grouping enough memory cells together in this manner to store each “1” and “0” bit, the grouped memory cells are able to retain a sufficient total electric charge as a group to properly store each bit even when individual memory cells in the group are unable to do so.

Abstract: A multi-stand block for a rolling mill comprises a plurality of roll stands alternately arranged on opposite sides of a pass line along which a product is rolled in a downstream direction from an entry end to an exit end of the block. Drive shafts are provided on opposite sides of the pass line. The drive shafts comprise coaxial segments interconnected by couplings, with each roll stand being connected to a respective one of the line shaft segments. A block drive is connected to the line shafts at the upstream end of the block, and the couplings are selectively disconnectable to mechanically isolate any downstream line shaft segments and the roll stands connected thereto from the block drive.

Abstract: A shear is disclosed for subdividing an elongated product moving longitudinally in a horizontal plane. The shear includes upper and lower continuously rotating blades respectively coacting in a radially overlapping relationship at first and second laterally disposed cutting zones. An upstream switch operates to divert the product laterally across the cutting zones to separate a leading end from an intermediate section in the first cutting zone, and to separate a trailing end from the intermediate section in the second cutting zone.

Abstract: An integrated circuit includes an array of memory cells, storage circuits and a write circuit coupled to the array, and a control circuit coupled to the array and write circuit. The write circuit is operable to receive initial test data and mask data. The control circuit is operable to enable the write circuit to write the initial test data to the cells, to receive an address of one of the cells, to enable the write circuit if the addressed cell is dormant to write the mask data to the storage circuit coupled to the cell such that the storage circuit stores the mask data, and to allow reading of the cell such that if the cell is dormant, then the storage circuit provides as a read value the stored mask data, and such that if the cell is live, then the storage circuit provides as the read value data that is stored in the cell.

Abstract: An apparatus is disclosed for receiving a helical formation of rings of hot rolled steel rod emerging from a laying head, and for depositing the rings on a conveyor for continued transport away from the laying head. The apparatus operates to engage and propel lower portions of the rings towards the conveyor at a first rate of travel, while engaging and propelling upper portions of the rings towards the conveyor at a second rate of travel. The first and second rates of travel are different and selected to cause the rings to topple onto the conveyor in an overlapping offset pattern.

Abstract: A method of continuously rolling a ferrous workpiece into a finished round, comprising rolling the workpiece in successive first and second roll passes at an elevated temperature of between about 650 to 1000° C., the first and second roll passes each being defined by two work rolls and being dimensioned to effect a combined reduction in the cross sectional area of the workpiece of at least about 20-55%, with an accompanying effective strain pattern dominated by a concentration of maximum effective strain at a central region of the cross sectional area; and while the effective strain pattern remains dominated by a concentration of maximum effective strain at a central region of the cross section, continuing to roll the workpiece in at least third and fourth consecutive roll passes, each of the third and fourth roll passes being defined by at least three rolls and being sized to effect a combined reduction in the cross sectional area of the workpiece of not more than about 4-25%.

Abstract: A memory device test circuit and method are described. These operate to maintain a local phase signal active over multiple row activate commands. As a result, an arbitrary number of word lines may be activated together, in an arbitrary order and in arbitrary locations, in response to user-programmable instructions. This allows test sequences to be tailored after the memory device has been designed and can greatly reduce testing times for memory devices.

Abstract: An integrated circuit memory device has a plurality of nonvolatile programmable elements which are used to store a pass/fail status bit at selected milestones in a test sequence. At selected points in the test process an element may be programmed to indicate that the device has passed the tests associated with the selected point in the process. Prior to performing further tests on the device, the element is read to verify that it passed previous tests in the test process. If the appropriate elements are not programmed, the device is rejected. A rejected device may be retested according to the previous test steps. Laser fuses, electrically programmable fuses or antifuses are used to store test results. The use of electrically writeable nonvolatile memory elements allows for programming of the elements after the device has been packaged.

Abstract: An adaptive hydraulic engine mount for mounting an engine to a frame of a motor vehicle includes a pumping chamber and reservoir filled with damping fluid and an orifice track or damping channel communicating the pumping chamber with the reservoir. A decoupling diaphragm responds to pressure level in a control cavity to control pumping of damping fluid through the damping channel, thereby controlling the dynamic stiffness of the mount. Upon actuation of a control valve, the pressure level in the control cavity is changed to achieve a level of damping greater than the low damping level. According to another embodiment of the invention, the control cavity can be communicated with engine vacuum to achieve maximum damping, or air may be trapped in the control cavity to achieve an intermediate level of damping, or the control cavity may be communicated to atmosphere to provide low levels of damping.