Abstract: An integrated circuit memory device has a plurality of nonvolatile programmable elements which are used to store a pass/fail status bit at selected milestones in a test sequence. At selected points in the test process an element may be programmed to indicate that the device has passed the tests associated with the selected point in the process. Prior to performing further tests on the device, the element is read to verify that it passed previous tests in the test process. If the appropriate elements are not programmed, the device is rejected. A rejected device may be retested according to the previous test steps. Laser fuses, electrically programmable fuses or antifuses are used to store test results. The use of electrically writeable nonvolatile memory elements allows for programming of the elements after the device has been packaged.

Abstract: A system for cooling a hot rolled steel product at a retarded cooling rate comprises a laying head for forming the product into a continuous series of rings. A conveyor receives the rings from the laying head at a receiving station and transports the rings in a non-concentric overlapping pattern through a cooling zone to a reforming station at which the rings are delivered from the conveyor and gathered into upstanding coils. The rings are covered with a granular insulation material while being transported through the cooling zone.

Abstract: A DRAM array is repairable when the array includes memory cells that are defective because their storage capacitors are unable to retain a sufficient electric charge to properly store “1” and “0” bits. To repair the array, both even and odd row decoders in the array are permanently enabled so that each row address the array receives causes the even row decoder to energize at least one even word line and the odd row decoder to energize at least one odd word line. As a result, at least two memory cells are accessed for each row address so that each “1” or “0” bit is stored as an electric charge in at least two memory cells. By grouping enough memory cells together in this manner to store each “1” and “0” bit, the grouped memory cells are able to retain a sufficient total electric charge as a group to properly store each bit even when individual memory cells in the group are unable to do so.

Abstract: Round bars are successively rolled through first and second roll passes. Each roll pass is defined by a pair of work rolls having cylindrical rolling surfaces with notches therein extending transversely and obliquely with respect to the rolling line, and with the roll axes defining the second roll pass being offset at 90 with respect to the roll axes defining the first roll pass. The first pair of work rolls is arranged to configure the round bar into an intermediate process section having flat parallel first sides with first ribs protruding therefrom, and the second pair of work rolls is arranged to reconfigure the process section into a finished concrete reinforcing element having flat parallel sides which are perpendicular to the first parallel sides and which have second ribs protruding therefrom.

Abstract: A memory device test circuit and method are described. These operate to maintain a local phase signal active over multiple row activate commands. As a result, an arbitrary number of word lines may be activated together, in an arbitrary order and in arbitrary locations, in response to user-programmable instructions. This allows test sequences to be tailored after the memory device has been designed and can greatly reduce testing times for memory devices.

Abstract: A DRAM array is repairable when the array includes memory cells that are defective because their storage capacitors are unable to retain a sufficient electric charge to properly store “1” and “0” bits. To repair the array, both even and odd row decoders in the array are permanently enabled so that each row address the array receives causes the even row decoder to energize at least one even word line and the odd row decoder to energize at least one odd word line. As a result, at least two memory cells are accessed for each row address so that each “1” or “0” bit is stored as an electric charge in at least two memory cells. By grouping enough memory cells together in this manner to store each “1” and “0” bit, the grouped memory cells are able to retain a sufficient total electric charge as a group to properly store each bit even when individual memory cells in the group are unable to do so.

Abstract: An integrated circuit includes an array of memory cells, storage circuits and a write circuit coupled to the array, and a control circuit coupled to the array and write circuit. The write circuit is operable to receive initial test data and mask data. The control circuit is operable to enable the write circuit to write the initial test data to the cells, to receive an address of one of the cells, to enable the write circuit if the addressed cell is dormant to write the mask data to the storage circuit coupled to the cell such that the storage circuit stores the mask data, and to allow reading of the cell such that if the cell is dormant, then the storage circuit provides as a read value the stored mask data, and such that if the cell is live, then the storage circuit provides as the read value data that is stored in the cell.

Abstract: An apparatus for receiving a continuous series of rings of a hot rolled product includes: a) a portable container having: i) a vertically disposed cylindrical side wall open at its upper and lower ends; ii) a base at the lower end of the side wall configured to removably locate the container at a coil forming station; iii) a horizontal shelf projecting inwardly from the interior of the side wall; and iv) a central core supported by the shelf, the core being spaced inwardly from the interior of the side wall to define an annular chamber therebetween, the shelf having access openings therein communicating with the chamber; b) an elevator platform at the coil forming station having support members configured and arranged to pass through the access openings in the shelf; and c) a mechanism for vertically adjusting the elevator platform to move its support members through the access openings in the shelf between raised operative positions at which the support members project into the annular chamber to supp

Abstract: A rolling mill has roughing, intermediate and finishing roll stands on a first side of a billet reheating furnace, and a breakdown mill on an opposite second side of the furnace. Billets are heated to an elevated rolling temperature in the furnace and are then ejected to the second side of the furnace for rolling in the breakdown mill before being directed back through the furnace for continued rolling into finished products at the first side of the furnace in the roughing, intermediate and finishing roll stands.

Abstract: A roll stand for a rolling mill, comprising: a support structure adapted to be fixed at a selected location along a mill center line. First and second work rolls are configured and arranged to roll products directed therebetween. The first work roll has roll necks journalled for rotation in bearings contained in first chocks, and the second work roll likewise has roll necks journalled for rotation in bearings contained in second chocks, with the first and second chocks of the work rolls being arranged in pairs located on opposite sides of the mill center line. The first and second chocks of each pair are connected to the support structure for pivotal movement respectively about parallel first and second connecting axes which extend in parallel relationship with respect to the axes of the rolls and orthogonally with respect to the mill center line.

Abstract: An integrated circuit includes an array of memory cells, storage circuits and a write circuit coupled to the array, and a control circuit coupled to the array and write circuit. The write circuit is operable to receive initial test data and mask data. The control circuit is operable to enable the write circuit to write the initial test data to the cells, to receive an address of one of the cells, to enable the write circuit if the addressed cell is dormant to write the mask data to the storage circuit coupled to the cell such that the storage circuit stores the mask data, and to allow reading of the cell such that if the cell is dormant, then the storage circuit provides as a read value the stored mask data, and such that if the cell is live, then the storage circuit provides as the read value data that is stored in the cell.

Abstract: An integrated circuit memory device has a plurality of nonvolatile programmable elements which are used to store a pass/fail status bit at selected milestones in a test sequence. At selected points in the test process an element may be programmed to indicate that the device has passed the tests associated with the selected point in the process. Prior to performing further tests on the device, the element is read to verify that it passed previous tests in the test process. If the appropriate elements are not programmed, the device is rejected. A rejected device may be retested according to the previous test steps. Laser fuses, electrically programmable fuses or antifuses are used to store test results. The use of electrically writeable nonvolatile memory elements allows for programming of the elements after the device has been packaged.

Abstract: A semiconductor device includes a plurality of conductive layers that are formed on the substrate. Two electrically intercoupled sections of a read-only storage element, such as a fuse element, which together compose the storage element, are each formed in a different one of the conductive layers. The storage element has a storage state, and each section has a conductivity. One can change the storage state of the storage element by changing the conductivity of one of the sections. Additionally, multiple storage elements may be coupled in parallel to form a storage module. Each of the storage elements of the storage module may include multiple storage sections that are each formed in a different conductive layer. The storage elements may store the version number of the mask set used to form the semiconductor device. Alternatively, a conductive layer is formed on a substrate, and one or more read-only storage elements are formed in the conductive layer.

Abstract: A method and apparatus for finish rolling long products such as bars, rods and the like, comprising: in a first operational mode, rolling the products through a finishing block and a reducing sizing mill arranged on a primary pass line; and in a second operational mode, diverting the products from the primary pass line to a secondary pass line bypassing the finishing block and then back to the primary pass line for rolling in the reducing sizing mill. Optionally and preferably, a cooling unit is shifted between the primary and secondary pass lines to cool products being rolled in each operational mode.

Abstract: A system for controlling front and tail end gauge of a continuous hot rolled product in a rolling mill includes first and second individually driven roll stands arranged successively along said pass line in advance of a group of roll stands. A controller adjusts the operating speed relationship between the first and second individually driven roll stands to achieve an increased level of tension in the front and tail end segments of the product passing between the first and second individually driven roll stands. The increased level of tension results in the decrease in product cross sectional area sufficient to compensate for the lack of cross sectional area reduction resulting from the absence of interstand tension experienced by said front and tail end segments while being rolled in the group of roll stands.

Abstract: Operation control circuitry for altering a sequence of internal memory operations in a memory device while in a test mode. The operation control circuitry includes a code circuit for providing an operation code in accordance to a user programmable code. An operation control circuit generates operation control signals in response to receiving command signals from a command circuit included in the operation control circuitry. The operation control signals generated by the operation control circuit control the occurrence of the internal memory operations according to an operation code.

Abstract: A system is disclosed for applying a liquid lubricant to first and second components enclosed in a housing, with the lubricant applied to the second components being exposed to contamination by a liquid coolant applied to the exterior of the housing, and with the lubricant applied to the first components being substantially isolated from the liquid coolant. The system includes a partition internally subdividing the housing into a first chamber containing the first components and a second chamber containing the second components. Lubricant is delivered from a storage tank to the housing for application to the first and second components. A first conduit network communicates with the first chamber for returning the lubricant applied to the first components to the storage tank, and a second conduit network communicates with the second chamber for returning lubricant applied to the second components to the storage tank.

Abstract: A DRAM array is repairable when the array includes memory cells that are defective because their storage capacitors are unable to retain a sufficient electric charge to properly store "1" and "0" bits. To repair the array, both even and odd row decoders in the array are permanently enabled so that each row address the array receives causes the even row decoder to energize at least one even word line and the odd row decoder to energize at least one odd word line. As a result, at least two memory cells are accessed for each row address so that each "1" or "0" bit is stored as an electric charge in at least two memory cells. By grouping enough memory cells together in this manner to store each "1" and "0" bit, the grouped memory cells are able to retain a sufficient total electric charge as a group to properly store each bit even when individual memory cells in the group are unable to do so.

Abstract: A DRAM array is repairable when the array includes memory cells that are defective because their storage capacitors are unable to retain a sufficient electric charge to properly store "1" and "0" bits. To repair the array, both even and odd row decoders in the array are permanently enabled so that each row address the array receives causes the even row decoder to energize at least one even word line and the odd row decoder to energize at least one odd word line. As a result, at least two memory cells are accessed for each row address so that each "1" or "0" bit is stored as an electric charge in at least two memory cells. By grouping enough memory cells together in this manner to store each "1" and "0" bit, the grouped memory cells are able to retain a sufficient total electric charge as a group to properly store each bit even when individual memory cells in the group are unable to do so.

Abstract: A memory device test circuit and method are described. These operate to maintain a local phase signal active over multiple row activate commands. As a result, an arbitrary number of word lines may be activated together, in an arbitrary order and in arbitrary locations, in response to user-programmable instructions. This allows test sequences to be tailored after the memory device has been designed and can greatly reduce testing times for memory devices.